公开(公告)号：US06510082B1

公开(公告)日：2003-01-21

申请号：US09999869

申请日：2001-10-23

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/28

摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

摘要翻译： 公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。 该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线， 其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。 该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流 在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

公开(公告)号：US06370061B1

公开(公告)日：2002-04-09

申请号：US09884583

申请日：2001-06-19

申请人： Santosh K. Yachareni ,  Kazuhiro Kurihara ,  Binh Q. Le ,  Michael S. C. Chung

发明人： Santosh K. Yachareni ,  Kazuhiro Kurihara ,  Binh Q. Le ,  Michael S. C. Chung

IPC分类号： G11C1634

CPC分类号： G11C16/3459 ,  G11C16/04 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the invention, an exemplary system and method are presented to apply a varying characterization signal operably through a high breakdown voltage periphery donut transistor and wordline drive transistors, which are driven into saturation by a boosted gate voltage which is higher than the applied varying characterization signal, in a manner which provides for the accurate determination of the VT of the core cells, through the comparison of the conduction in a reference cell to that of the conduction in a core cell produced by a varying characterization signal applied to the core cell gate.

摘要翻译： 本发明涉及闪存系统和确定核心单元的阈值电压的方法。 在一个示例性系统中，提供了表征编程单元阵列的阈值电压分布的高端的方法。 根据本发明，提出了一种示例性的系统和方法，以通过高耐压周边环形晶体管和字线驱动晶体管可操作地应用变化的特征信号，该晶体管和字线驱动晶体管通过高于施加的变化的升压栅极电压而被驱动为饱和 表征信号，以提供核心单元的VT的精确确定的方式，通过比较参考单元中的导通与通过施加到核心单元的变化表征信号产生的核心单元中的导通的比较 门。

公开(公告)号：US06493266B1

公开(公告)日：2002-12-10

申请号：US09829193

申请日：2001-04-09

申请人： Santosh K. Yachareni ,  Darlene G. Hamilton ,  Binh Q. Le ,  Kazuhiro Kurihara

发明人： Santosh K. Yachareni ,  Darlene G. Hamilton ,  Binh Q. Le ,  Kazuhiro Kurihara

IPC分类号： G11C1134

CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/3404 ,  G11C16/3436

摘要： A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.

摘要翻译： 公开了用于存储器单元软程序和软程序验证，调整或校正目标最小值与最大值之间的阈值电压的方法和系统，其可以与双位存储器单元架构相关联使用。 该方法包括将一个参考电压信号施加到过擦除的核心单元，以及将不同的参考电压信号施加到参考单元，比较由每个产生的两个电流，选择性地验证单元的一个或多个位的适当的软编程，确定 双位存储单元被正确软编程。 该方法还可以包括在对该小区的至少一个或多个比特进行选择性软编程之后，选择性地重新验证小区的适当的软编程。

公开(公告)号：US06525969B1

公开(公告)日：2003-02-25

申请号：US09928059

申请日：2001-08-10

申请人： Kazuhiro Kurihara ,  Santosh K. Yachareni

发明人： Kazuhiro Kurihara ,  Santosh K. Yachareni

IPC分类号： G11C1606

CPC分类号： G11C16/28 ,  G11C7/12 ,  G11C16/0491 ,  G11C16/24 ,  G11C2207/063

摘要： Methods and apparatus are disclosed for reading memory cells in a virtual ground memory core, wherein a memory cell is selected to be read and an adjacent memory cell is precharged so as to mitigate leakage current associated with the adjacent cell. Decoder circuitry and methods are disclosed for selecting the memory cell to be read and the adjacent cell to be precharged, which may be used in single bit and dual bit memory devices, and which provide drain-side or source-side current sensing in the read operation.

摘要翻译： 公开了用于读取虚拟地址存储器核心中的存储器单元的方法和装置，其中选择存储器单元进行读取，并且相邻存储器单元被预充电以便减轻与相邻单元相关联的泄漏电流。 公开了用于选择要读取的存储器单元和要预充电的相邻单元的解码器电路和方法，其可以在单位和双位存储器件中使用，并且在读取中提供漏极侧或源极电流感测 操作。

公开(公告)号：US06208561B1

公开(公告)日：2001-03-27

申请号：US09593303

申请日：2000-06-13

申请人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/08

摘要： An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

摘要翻译： 提供了一种用于降低闪存X解码器中的电容负载以便精确地将电压控制为选择的字线和块选择线的装置和方法。 解码结构分别将第一升压电压施加到字线N阱区域，并将第二升压电压施加到所选择的字线，以便由于与字线N阱区域相关联的重电容性负载而减小所选字线上的容性负载。 解码结构还将第三升压电压施加到选择栅极N阱区域，并将第四升压电压施加到块选择线，以便由于与选择栅极N相关联的重电容负载而减小块选择线上的电容负载， 井区。 因此，由于其电容加载路径非常小，所以可以在所选字线处快速创建精确的电压。

公开(公告)号：US20140020967A1

公开(公告)日：2014-01-23

申请号：US13816415

申请日：2012-03-13

申请人： Kouji Nishiyama ,  Kazuhiro Kurihara ,  Tetsuya Okuyama

发明人： Kouji Nishiyama ,  Kazuhiro Kurihara ,  Tetsuya Okuyama

IPC分类号： B66F9/075

CPC分类号： B66F9/07572 ,  B60K1/04 ,  B60K2001/0422 ,  B60K2001/0455 ,  B60K2001/0466 ,  B60Y2200/15 ,  B66F9/0754

摘要： A battery-powered forklift including a fork placed at an anterior portion of a vehicle body, and a counter weight placed at a posterior portion of the vehicle body, the battery-powered forklift running by electric power of a battery mounted on the vehicle body, wherein a concave portion that is open in a longitudinal direction is formed at an upper surface of the counter weight, the battery is mounted on a position above a rear wheel of the vehicle body while at least a part of the battery overlaps with the counter weight, and the battery is removable toward a rear of the vehicle body through the concave portion of the counter weight.

摘要翻译： 一种电池供电的叉车，包括放置在车身前部的叉子，以及放置在车体后部的配重，所述电池供电的叉车由安装在车体上的电池的电力运行， 其特征在于，在所述配重的上表面形成有在长度方向上开口的凹部，所述电池被安装在所述车体的后轮上方的位置，同时所述电池的至少一部分与所述配重重叠 并且电池通过配重的凹部朝向车体的后部移除。

公开(公告)号：US08379472B2

公开(公告)日：2013-02-19

申请号：US13155278

申请日：2011-06-07

申请人： Hiroaki Wada ,  Kazuhiro Kurihara

发明人： Hiroaki Wada ,  Kazuhiro Kurihara

IPC分类号： G11C5/14

CPC分类号： G11C16/30 ,  G11C5/147 ,  H04N5/23241

摘要： The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

公开(公告)号：US07903473B2

公开(公告)日：2011-03-08

申请号：US12508319

申请日：2009-07-23

申请人： Hiroki Murakami ,  Kazuhiro Kurihara

发明人： Hiroki Murakami ,  Kazuhiro Kurihara

IPC分类号： G11C16/04

CPC分类号： G11C11/413 ,  G11C16/102 ,  G11C16/105

摘要： A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

公开(公告)号：US07206241B2

公开(公告)日：2007-04-17

申请号：US11126558

申请日：2005-05-11

申请人： Kazunari Kido ,  Yasushi Kasa ,  Minoru Yamashita ,  Kazuhiro Kurihara ,  Hiroaki Wada

发明人： Kazunari Kido ,  Yasushi Kasa ,  Minoru Yamashita ,  Kazuhiro Kurihara ,  Hiroaki Wada

IPC分类号： G11C7/02

CPC分类号： G11C16/12 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3445 ,  G11C16/3459

摘要： The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

摘要翻译： 本发明的半导体器件包括至少一个编程状态的虚拟单元，其近似位于参考单元阵列的边缘。 因此，当读取参考单元阵列的边缘上的单元的数据时，泄漏电流不流动。 位于参考单元阵列中心周围的存储单元具有编程状态的相邻单元，并且当从所有参考单元读出数据时，可以防止泄漏电流。 因此，能够稳定地供给基准电流。

公开(公告)号：US06975543B2

公开(公告)日：2005-12-13

申请号：US11085133

申请日：2005-03-22

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/28 ,  G11C16/34

CPC分类号： G11C16/28 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3454

摘要： A nonvolatile semiconductor memory device includes nonvolatile memory cells each configured to store 2-bit information per memory cell, and a control circuit configured to verify with a first threshold one or more bits subjected to writing of new data and to verify with a second threshold one or more bits subjected to refreshing of existing data in a program operation that performs the writing of new data and the refreshing of existing data simultaneously with respect to the nonvolatile memory cells, the second threshold being lower than the first threshold.

摘要翻译： 非易失性半导体存储器件包括非易失性存储单元，每个非易失性存储单元被配置为存储每个存储单元的2位信息;以及控制电路，被配置为以第一阈值验证经受新数据写入的一个或多个位，并且以第二阈值1 或更多位在执行新数据的写入和与非易失性存储单元同时刷新现有数据的程序操作中刷新现有数据，第二阈值低于第一阈值。