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公开(公告)号：US06181605B2
公开(公告)日：2001-01-30
申请号：US09414750
申请日：1999-10-06
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/3436 , G11C16/3459
摘要： A technique to determine whether multiple memory cells are programmed or erased. After a program or erase operation, respective program or erase verify operations are performed. A logical gate is coupled to measure the state of each memory cell. When all memory cells selected to be programmed or erased are programmed or erased then the output of the logical gate indicates successful program or erase verify. Thus, by using a single logical gate coupled to measure the states of multiple memory cells, only the output of the logical gate need be measured to determine successful program or erase verification of multiple memory cells.
摘要翻译： 确定多个存储器单元是否被编程或擦除的技术。 在编程或擦除操作之后，执行相应的编程或擦除验证操作。 耦合逻辑门来测量每个存储单元的状态。 当所有被选择被编程或擦除的存储单元被编程或擦除时，逻辑门的输出指示成功的程序或擦除验证。 因此，通过使用耦合以测量多个存储器单元的状态的单个逻辑门，仅需要测量逻辑门的输出以确定多个存储单元的成功编程或擦除验证。
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2.发明授权Method and apparatus for adjusting on-chip current reference for EEPROM sensing 有权用于调整EEPROM感应的片内电流参考的方法和装置公开(公告)号：US06525966B1
公开(公告)日：2003-02-25
申请号：US10010985
申请日：2001-12-05
IPC分类号： G11C1606
摘要： Method and apparatus for a memory circuit having a sense amplifier circuit having a sensing amplifier connected to read the data content output of a memory cell where the sense amplifier circuit includes a current source transistor having a gate terminal and having a drain terminal connected to a voltage supply and having a source terminal connected to the sensing amplifier, with a selectable source current in order to account for variation from a desired source current due to variations in the designed source current transistor performance parameters.
摘要翻译： 一种具有读出放大器电路的存储电路的方法和装置，该读出放大器电路具有连接到读出存储单元的数据内容输出的感测放大器，其中读出放大器电路包括具有栅极端子并具有连接到电压的漏极端子的电流源晶体管 提供并具有连接到感测放大器的源极端子，具有可选择的源极电流，以便考虑到由于设计的源极电流晶体管性能参数的变化而导致的期望源极电流的变化。
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公开(公告)号：US06545912B1
公开(公告)日：2003-04-08
申请号：US09727656
申请日：2000-11-30
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C16/344 , G11C29/50
摘要： A method is provided to determine erase threshold voltages of memory transistors and thereby identify unusable memory transistors. A voltage is applied to the common source of a selected memory transistor and gradually incremented until a logical HIGH bit is read as a logical LOW bit. By iteratively incrementing Vbias, the erase threshold voltage for each memory transistor can be determined. In one process, the erase threshold voltage for each memory transistor in a memory device is determined and then the memory device is put under stress tests to simulate normal operative conditions. After the stress tests, the erase threshold voltage of each memory transistor can be once again determined to ascertain the change in the erase threshold voltage, i.e., the data retention characteristic, of each memory transistor.
摘要翻译： 提供了一种方法来确定存储晶体管的擦除阈值电压，从而识别不可用的存储晶体管。 电压被施加到所选择的存储晶体管的公共源，并逐渐增加，直到逻辑高位被读为逻辑低位。 通过迭代地增加Vbias，可以确定每个存储晶体管的擦除阈值电压。 在一个过程中，确定存储器件中每个存储晶体管的擦除阈值电压，然后将存储器件置于压力测试中以模拟正常工作状态。 在应力测试之后，可以再次确定每个存储晶体管的擦除阈值电压，以确定每个存储晶体管的擦除阈值电压（即数据保持特性）的变化。
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公开(公告)号：US06185130B2
公开(公告)日：2001-02-06
申请号：US09420209
申请日：1999-10-18
IPC分类号： G11C1606
CPC分类号： G11C16/24 , G11C5/147 , G11C16/3436 , G11C29/12
摘要： A programmable reference current source used with a memory array during test and user modes to program or erase verify. The reference current source is programmable so that optimal reference currents can be determined during test mode. A value representing the optimal reference current is stored so that the reference current source provides the determined reference current during user mode.
摘要翻译： 在测试期间与存储器阵列一起使用的可编程参考电流源，并且用户模式编程或擦除验证。 参考电流源可编程，以便在测试模式下可以确定最佳的参考电流。 存储表示最佳参考电流的值，使得参考电流源在用户模式期间提供确定的参考电流。
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5.发明授权Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same 有权位线偏置方法，用于消除非易失性存储器件和采用其中的存储器件中的程序干扰
公开(公告)号：US5978267A
公开(公告)日：1999-11-02
申请号：US175647
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael Van Buskirk , Shane C. Hollmer , Michael S. C. Chung , Binh Quang Le , Vincent Leung , Shoichi Kawamura , Masaru Yano
发明人： Pau-Ling Chen , Michael Van Buskirk , Shane C. Hollmer , Michael S. C. Chung , Binh Quang Le , Vincent Leung , Shoichi Kawamura , Masaru Yano
CPC分类号： G11C16/10 , G11C16/0483 , G11C7/12
摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.
摘要翻译： 在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。 在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。
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6.发明授权
公开(公告)号：US5995417A
公开(公告)日：1999-11-30
申请号：US175646
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
发明人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.
摘要翻译： 非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页 被擦除和擦除验证。 擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他 连接到未选择用于页面擦除的字线的MOS晶体管。 在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。
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7.发明授权Method and apparatus for detecting exposure of a semiconductor circuit to ultra-violet light 有权用于检测半导体电路对紫外光的曝光的方法和装置公开(公告)号：US06970386B2
公开(公告)日：2005-11-29
申请号：US10378414
申请日：2003-03-03
申请人： Shane C. Hollmer
发明人： Shane C. Hollmer
摘要： A method and apparatus are disclosed for detecting if a semiconductor circuit has been exposed to ultra-violet light. An ultra-violet light detection circuit detects exposure to ultra-violet light and will automatically activate a security violation signal. The security violation signal may optionally initiate a routine to clear sensitive data from memory or prevent the semiconductor circuit from further operation. The ultra-violet light detection circuit detects whether a semiconductor circuit has been exposed to ultra-violet light, for example, by employing a dedicated mini-array of non-volatile memory cells. At least two active bit lines, blprg and bler, are employed corresponding to program and erase, respectively. One of the bit lines is only programmable and the other bit line is only eraseable. Generally, all of the bits in the dedicated non-volatile memory array are initially in approximately the same state, which could be erased, programmed or somewhere in between. An offset current is added to one bit line and a change in the resulting current difference is used to detect an exposure to ultra-violet light.
摘要翻译： 公开了一种用于检测半导体电路是否已经暴露于紫外光的方法和装置。 紫外光检测电路检测到紫外光的曝光，并自动激活安全违规信号。 安全违规信号可以可选地启动例程以从存储器清除敏感数据或防止半导体电路进一步操作。 紫外光检测电路例如通过采用非易失性存储单元的专用微型阵列来检测半导体电路是否已经暴露于紫外光。 对应于编程和擦除分别使用至少两个有效位线blprg和bler。 其中一个位线只能编程，另一个位线只能擦除。 通常，专用非易失性存储器阵列中的所有位最初处于大致相同的状态，这可能被擦除，编程或其间的某处。 偏移电流被添加到一个位线，并且所得到的电流差的变化用于检测对紫外光的曝光。
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8.发明授权Select transistor architecture for a virtual ground non-volatile memory cell array 失效选择用于虚拟地面非易失性存储单元阵列的晶体管架构公开(公告)号：US06477083B1
公开(公告)日：2002-11-05
申请号：US09686685
申请日：2000-10-11
IPC分类号： G11C1604
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , G11C16/14 , H01L27/115
摘要： A bit line selector for a virtual ground non-volatile read only memory (“NROM”) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to the bit line and the channel width is parallel to the bit line. Subsequent reduction in the bit line pitch does not affect the channel width of the select transistors or their drive current.
摘要翻译： 公开了用于虚拟非易失性只读存储器（“NROM”）单元阵列的位线选择器。 选择器晶体管被定向成使得沟道长度垂直于位线并且沟道宽度平行于位线。 位线间距的随后减小不会影响选择晶体管的沟道宽度或其驱动电流。
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9.发明授权Embedded methodology to program/erase reference cells used in sensing flash cells 有权用于编程/擦除用于感测闪存单元的参考单元的嵌入式方法公开(公告)号：US06418054B1
公开(公告)日：2002-07-09
申请号：US09387421
申请日：1999-08-31
申请人： Shane C. Hollmer
发明人： Shane C. Hollmer
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C16/10 , G11C16/3454
摘要： Programming lines are attached to reference cells of a memory device. A state machine controls voltages and/or currents applied to the reference cells via the programming lines to program and verify a program state of the reference cells. The state machine utilizes existing array cell programming operations conducted by the programming lines to the reference cells. The utilization of internal circuitry of the memory device in the programming of reference cells reduces the sort and test time of the memory device. The memory device may be a flash memory device or any device having reference cells, and the reference cells may be of any configuration or structure, including nitride layer cells.
摘要翻译： 编程线连接到存储器件的参考单元。 状态机通过编程线控制施加到参考单元的电压和/或电流，以对参考单元的编程状态进行编程和验证。 状态机利用编程线对参考单元进行的现有阵列单元编程操作。 在参考单元的编程中利用存储器件的内部电路减少了存储器件的分类和测试时间。 存储器件可以是闪存器件或具有参考单元的任何器件，并且参考单元可以是包括氮化物层单元的任何配置或结构。
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公开(公告)号：US06269025B1
公开(公告)日：2001-07-31
申请号：US09500699
申请日：2000-02-09
申请人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
发明人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C1604
摘要： A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.
摘要翻译： 如果编程或擦除时间过长，存储系统可以调整程序或擦除电压。 存储器系统至少包括存储器单元，电压值存储器件，电压源和电压调节电路。 电压值存储装置存储电压值。 电压源接收并将电压值转换为电压。 电压源将电压施加到至少一个存储单元。 电压调节电路也耦合以接收存储的电压值。 电压调节电路使用电压值来确定编程或擦除至少一个存储单元所需的时间。 如果编程或擦除至少一个存储单元的时间过长，则电压调节电路增加存储在电压值存储装置中的电压值。
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