公开(公告)号：US09607996B2

公开(公告)日：2017-03-28

申请号：US15037077

申请日：2014-08-15

申请人： Sharp Kabushiki Kaisha

发明人： Sumio Katoh ,  Naoki Ueda

IPC分类号： H01L29/10 ,  H01L27/112 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/10 ,  G09G3/36 ,  H01L29/417

CPC分类号： H01L27/11206 ,  G02F1/1368 ,  G09G3/3655 ,  G09G2300/0426 ,  G09G2300/08 ,  G09G2300/0842 ,  H01L27/101 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/41733 ,  H01L29/78678 ,  H01L29/7869

摘要： A semiconductor device includes a memory transistor (10A) which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg. The memory transistor (10A) includes a gate electrode (3), a metal oxide layer (7), a gate insulating film (5), and source and drain electrodes. The drain electrode (9d) has a multilayer structure which includes a first drain metal layer (9d1) and a second drain metal layer (9d2), the first drain metal layer (9d1) being made of a first metal whose melting point is not less than 1200° C., the second drain metal layer (9d2) being made of a second metal whose melting point is lower than that of the first metal. Part P of the drain electrode 9d extends over both the metal oxide layer (7) and the gate electrode (3) when viewed in a direction normal to a surface of the substrate. The part (P) of the drain electrode (9d) includes the first drain metal layer (9d1) and does not include the second drain metal layer (9d2).

公开(公告)号：US20190295473A1

公开(公告)日：2019-09-26

申请号：US15935123

申请日：2018-03-26

申请人： Sharp Kabushiki Kaisha

发明人： Tong Lu ,  Michael James Brownlow ,  Tim Michael Smeeton ,  Naoki Ueda

IPC分类号： G09G3/3291 ,  G09G3/3266

摘要： A pixel circuit for a display device includes a drive transistor configured to control an amount of current to a light-emitting device depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor and a second terminal of the drive transistor, such that when the second transistor is in an on state the drive transistor becomes diode-connected such that the gate and the second terminal of the drive transistor are connected through the second transistor; a light-emitting device that is connected at a first node to a third terminal of the drive transistor and at a second node to a first voltage supply; a third transistor connected to the first node of the light-emitting device, which connects a data voltage to the first node of the light-emitting device; a fourth transistor that is connected between the second terminal of the drive transistor and a second voltage supply; and at least one capacitor having a first plate that is connected to the gate of the drive transistor and a second plate that is connectable to a reference signal. The pixel circuit is operable during a phase preceding the emission phase including applying a data voltage to the first node of the light-emitting device and the third terminal of the drive transistor, the data voltage being set so that a voltage across the light-emitting device is lower than a threshold voltage of the light emitting device.

公开(公告)号：US09859016B2

公开(公告)日：2018-01-02

申请号：US15038747

申请日：2014-08-26

申请人： Sharp Kabushiki Kaisha

发明人： Sumio Katoh ,  Naoki Ueda

IPC分类号： G11C11/00 ,  G11C17/18 ,  G11C13/00 ,  G11C17/16 ,  G11C19/28 ,  H01L27/105 ,  H01L27/112 ,  H01L29/24 ,  H01L29/786 ,  G02F1/1345 ,  G02F1/1368

CPC分类号： G11C17/18 ,  G02F1/13452 ,  G02F1/1368 ,  G02F2201/123 ,  G11C13/0007 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C19/28 ,  G11C2213/53 ,  H01L27/1052 ,  H01L27/11206 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696

摘要： A semiconductor device (1001) includes: a memory cell; and a writing control circuit (107), wherein the memory cell includes a memory transistor (10A) which has an active layer (7A), the active layer (7A) including a metal oxide, the memory transistor (10A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit (107) is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs≧Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (10A) and Vds is a drain-source voltage of the memory transistor (10A), whereby writing in the memory transistor (10A) is performed.

公开(公告)号：US09741308B2

公开(公告)日：2017-08-22

申请号：US15117507

申请日：2015-02-10

申请人： Sharp Kabushiki Kaisha

发明人： Masahiro Tomida ,  Naoki Ueda

IPC分类号： H01L29/786 ,  G02F1/1362 ,  G09G3/36 ,  G02F1/1368 ,  H01L29/417 ,  G02F1/133 ,  G02F1/1343 ,  H01L29/24 ,  H01L29/423 ,  H01L27/12 ,  G02F1/1345 ,  G02F1/1333

CPC分类号： G09G3/3648 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2201/123 ,  G02F2202/10 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2320/0214 ,  G09G2330/021 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3276 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： An active matrix substrate (100) includes a display region (R1) in which a plurality of pixels are provided and a frame region (R2) provided around the display region, the frame region including a plurality of peripheral circuit TFTs (5) which are constituents of a driving circuit, wherein each of the plurality of peripheral circuit TFTs includes a gate electrode (12), a source electrode (16), a drain electrode (18), and an oxide semiconductor layer (14), and in at least some of the plurality of peripheral circuit TFTs, a source connecting region (Rs) that is a connecting region between the oxide semiconductor layer and the source electrode and a drain connecting region (Rd) that is a connecting region between the oxide semiconductor layer and the drain electrode are asymmetrically provided.

公开(公告)号：US09583510B2

公开(公告)日：2017-02-28

申请号：US14910454

申请日：2014-07-24

申请人： Sharp Kabushiki Kaisha

发明人： Sumio Katoh ,  Naoki Ueda

IPC分类号： H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  G02F1/1362

CPC分类号： H01L27/1225 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78696

摘要： A semiconductor device (100A) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer; an oxide semiconductor layer (16) formed on the gate insulating layer; a second metal layer (18) formed on the oxide semiconductor layer; an interlayer insulating layer (22) formed on the second metal layer; and a transparent electrode layer (TE) including a transparent conductive layer (Tc). The oxide semiconductor layer includes a first portion (16a) and a second portion (16b) extending while crossing an edge of the gate electrode. The second metal layer includes a source electrode (18s) and a drain electrode (18d). The interlayer insulating layer does not include an organic insulating layer. The interlayer insulating layer includes a contact hole (22a) formed so as to overlap the second portion and an end of the drain electrode that is closer to the second portion. The transparent conductive layer (Tc) is in contact with the end of the drain electrode and the second portion of the oxide semiconductor layer in the contact hole.

摘要翻译： 半导体器件（100A）包括包括栅电极（12g）的第一金属层（12） 形成在所述第一金属层上的栅极绝缘层（14） 形成在所述栅极绝缘层上的氧化物半导体层（16） 形成在所述氧化物半导体层上的第二金属层（18） 形成在所述第二金属层上的层间绝缘层（22） 和包含透明导电层（Tc）的透明电极层（TE）。 氧化物半导体层包括在与栅电极的边缘交叉的同时延伸的第一部分（16a）和第二部分（16b）。 第二金属层包括源极（18s）和漏电极（18d）。 层间绝缘层不包括有机绝缘层。 层间绝缘层包括形成为与第二部分重叠的接触孔（22a）和漏电极的靠近第二部分的端部。 透明导电层（Tc）与漏电极的端部和接触孔中的氧化物半导体层的第二部分接触。

公开(公告)号：US20150243668A1

公开(公告)日：2015-08-27

申请号：US14434148

申请日：2013-10-15

申请人： SHARP KABUSHIKI KAISHA

发明人： Naoki Ueda ,  Sumio Katoh

IPC分类号： H01L27/112

CPC分类号： H01L27/11206 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/101

摘要： The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cell 1 includes a memory transistor Qm, and first and second selection transistors Q1 and Q2. During a writing operation, the memory transistor Qm and the first selection transistor Q1 are set to the ON state, and the second selection transistor Q2 is set to the OFF state. A writing current is flown to a series circuit of the memory transistor Qm and the first selection transistor Q1. The memory transistor Qm is transited from a first state that indicates a transistor characteristic to a second state that indicates an ohmic resistance characteristic. During a reading operation, the first selection transistor Q1 is set to the OFF state, the second selection transistor Q2 is set to the ON state, a voltage is applied to a series circuit of the memory transistor Qm and the second selection transistor Q2, and it is detected whether the memory transistor Qm is in the first state or the second state.

摘要翻译： 本发明提供了一种非易失性存储器件，其使用包括氧化物半导体的存储晶体管，能够以低功耗写入，而不会受到串联连接到存储晶体管的选择晶体管的劣化的影响。 存储单元1包括存储晶体管Qm以及第一和第二选择晶体管Q1和Q2。 在写入操作期间，存储晶体管Qm和第一选择晶体管Q1被设置为导通状态，并且第二选择晶体管Q2被设置为截止状态。 写入电流流到存储晶体管Qm和第一选择晶体管Q1的串联电路。 存储晶体管Qm从表示晶体管特性的第一状态转变为指示欧姆电阻特性的第二状态。 在读取操作期间，第一选择晶体管Q1被设置为截止状态，第二选择晶体管Q2被设置为导通状态，电压被施加到存储晶体管Qm和第二选择晶体管Q2的串联电路，以及 检测存储晶体管Qm是处于第一状态还是第二状态。

公开(公告)号：US12118947B2

公开(公告)日：2024-10-15

申请号：US18028710

申请日：2020-10-02

申请人： Sharp Kabushiki Kaisha

发明人： Nobuyuki Taya ,  Makoto Yokoyama ,  Naoki Ueda

IPC分类号： G09G3/3266 ,  G09G3/3233 ,  G11C19/28

CPC分类号： G09G3/3266 ,  G09G3/3233 ,  G11C19/287 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/041 ,  G09G2320/043

摘要： The scanning line drive circuit has a configuration in which a plurality of unit circuits are connected in multiple stages. A unit circuit includes: a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node; a second transistor having a second conductive terminal to which a second-level voltage is applied; a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor; a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied; and an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.

公开(公告)号：US11762247B2

公开(公告)日：2023-09-19

申请号：US16981447

申请日：2018-03-16

申请人： SHARP KABUSHIKI KAISHA

发明人： Junichi Yamada ,  Makoto Yokoyama ,  Naoki Ueda

IPC分类号： G02F1/1345 ,  H05K1/18 ,  H10K59/12

CPC分类号： G02F1/13452 ,  H05K1/189 ,  H10K59/12

摘要： Provided is a display device including a display panel which allows a curvature portion thereof to be narrowed near a terminal portion even when circuit blocks are arranged in the curvature portion.
For a data line in the form of a polyline consisting of a plurality of short straight line segments in a first curvature portion 12a of a display panel 10, as the distance from a terminal portion 16 increases, the slant angle of each straight line segment increases, the number of data lines d decreases, and hence the width of a data line area decreases. Accordingly, the number of unit circuit blocks 70 in a parallel circuit block 80 disposed in a circuit area can be increased by widening the circuit area in proportion to the decrease in the width of the data line area.

公开(公告)号：US10679558B2

公开(公告)日：2020-06-09

申请号：US16477555

申请日：2017-09-25

申请人： Sharp Kabushiki Kaisha

发明人： Naoki Ueda

IPC分类号： G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  H01L27/32

摘要： The present application discloses to provide a display device capable of displaying an image with a luminance depending on a data signal by controlling pulling of a gate voltage of a driving transistor occurring when a writing period starts and ends and a driving method of the display device.A pixel circuit including a compensation circuit compensating variation of a threshold value of a driving transistor is provided with a boost capacitor including a MOS capacitor between a node connected to a gate terminal of the driving transistor and a scanning line. A current value of a drive current is controlled by the driving transistor by using the pulling of the potential of the node being different between a case that a low level voltage is applied the scanning line connected to the boost capacitor and a case that a high level voltage is applied.

公开(公告)号：US10386684B2

公开(公告)日：2019-08-20

申请号：US15534197

申请日：2015-12-14

申请人： Sharp Kabushiki Kaisha

发明人： Kuniaki Okada ,  Seiichi Uchida ,  Naoki Ueda ,  Sumio Katoh

IPC分类号： G02F1/1368 ,  G02F1/1362 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1343 ,  H01L21/02 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66

摘要： A semiconductor device (100A) includes a thin film transistor (10), an inter-layer insulation layer (22) covering the thin film transistor, and a transparent conductive layer (24) formed on the inter-layer insulation layer. The metal oxide layer (16) of the thin film transistor includes a first portion (16a) overlapping the gate electrode (12) via a gate insulation layer (14) and a second portion (16b) not overlapping the gate electrode (12). The second portion (16b) crosses a different edge (e2) different from an edge (e1) of the drain electrode (18d) on a side of the first portion when viewed in the normal direction of the substrate (11). The inter-layer insulation layer has a contact hole (22a) disposed to overlap a part of the drain electrode (18d) and at least a part of the second portion (16b) of the metal oxide layer when viewed in the normal direction of the substrate. The transparent conductive layer (24) comes into contact with the drain electrode (18d), the second portion (16b), and the gate insulation layer (14) in the contact hole (22a).