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公开(公告)号：US20110318672A1
公开(公告)日：2011-12-29
申请号：US12824037
申请日：2010-06-25
申请人： Shem Ogadhoh , Raguraman Venkatesan , Kevin J. Hooker , Sungwon Kim , Bin Hu , Vivek Singh , Bikram Baidya , Prasad Narendra Atkar , Seongtae Jeong
发明人： Shem Ogadhoh , Raguraman Venkatesan , Kevin J. Hooker , Sungwon Kim , Bin Hu , Vivek Singh , Bikram Baidya , Prasad Narendra Atkar , Seongtae Jeong
摘要： Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.
摘要翻译： 这里描述的是要连续成像以在诸如半导体晶片的衬底上打印复合图案的一组掩模的掩模设计和建模。 本文进一步描述的是使用该组掩模对衬底进行双重图案化的方法。 这里还描述了一种基于掩模级别中的另一个的预测图案轮廓来校正掩模级中的一个的绘制图案的方法。 本文还描述了一种对光致抗蚀剂施加到非均匀衬底上的掩模级的抗蚀剂轮廓轮廓建模方法，以及预测两个掩模的布尔运算的抗蚀剂轮廓的方法。
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公开(公告)号：US08404403B2
公开(公告)日：2013-03-26
申请号：US12824037
申请日：2010-06-25
申请人： Shem Ogadhoh , Raguraman Venkatesan , Kevin J. Hooker , Sungwon Kim , Bin Hu , Vivek Singh , Bikram Baidya , Prasad Narendra Atkar , Seongtae Jeong
发明人： Shem Ogadhoh , Raguraman Venkatesan , Kevin J. Hooker , Sungwon Kim , Bin Hu , Vivek Singh , Bikram Baidya , Prasad Narendra Atkar , Seongtae Jeong
IPC分类号： G03F1/68
摘要： Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.
摘要翻译： 这里描述的是要连续成像以在诸如半导体晶片的衬底上打印复合图案的一组掩模的掩模设计和建模。 本文进一步描述的是使用该组掩模对衬底进行双重图案化的方法。 这里还描述了一种基于掩模级别中的另一个的预测图案轮廓来校正掩模级中的一个的绘制图案的方法。 本文还描述了一种对光致抗蚀剂施加到非均匀衬底上的掩模级的抗蚀剂轮廓轮廓建模方法，以及预测两个掩模的布尔运算的抗蚀剂轮廓的方法。
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公开(公告)号：US08778605B2
公开(公告)日：2014-07-15
申请号：US13762083
申请日：2013-02-07
申请人： Shem Ogadhoh , Raguraman Venkatesan , Kevin J. Hooker , Sungwon Kim , Bin Hu , Vivek Singh , Bikram Baidya , Prasad Narendra Atkar , Seongtae Jeong
发明人： Shem Ogadhoh , Raguraman Venkatesan , Kevin J. Hooker , Sungwon Kim , Bin Hu , Vivek Singh , Bikram Baidya , Prasad Narendra Atkar , Seongtae Jeong
摘要： Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.
摘要翻译： 这里描述的是要连续成像以在诸如半导体晶片的衬底上打印复合图案的一组掩模的掩模设计和建模。 本文进一步描述的是使用该组掩模对衬底进行双重图案化的方法。 这里还描述了一种基于掩模级别中的另一个的预测图案轮廓来校正掩模级中的一个的绘制图案的方法。 本文还描述了一种对光致抗蚀剂施加到非均匀衬底上的掩模级的抗蚀剂轮廓轮廓建模方法，以及预测两个掩模的布尔运算的抗蚀剂轮廓的方法。
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4.发明授权Measurement of a scattered light point spread function (PSF) for microelectronic photolithography 失效用于微电子光刻的散射光点扩散函数（PSF）的测量公开(公告)号：US07691544B2
公开(公告)日：2010-04-06
申请号：US11490924
申请日：2006-07-21
IPC分类号： G03F1/00
CPC分类号： G03F7/70941 , G03F1/44 , G03F7/70591
摘要： A scattered light point spread function is measured for use in fabricating microelectronic and micromechanical devices using photolithography. In one example, a photosensitive layer of a microelectronic substrate is exposed through a test mask, the test mask having a series of differently sized patterns, each pattern surrounding a central monitor feature, the differently sized patterns each being evenly distributed about its respective central monitor feature. An indication of the exposure of the photosensitive layer is measured for a plurality of the series of differently sized patterns. The exposure indication is compared to the pattern size. The comparison is fitted to a function and the function is applied in correcting photolithography mask layouts.
摘要翻译： 测量散射光点扩散函数用于使用光刻制造微电子和微机械器件。 在一个示例中，微电子衬底的感光层通过测试掩模曝光，测试掩模具有一系列不同大小的图案，每个图案围绕中央监视器特征，不同尺寸的图案均分布在其相应的中央监视器周围 特征。 测量多个不同尺寸图案的一系列感光层的曝光指示。 将曝光指示与图案尺寸进行比较。 该比较适用于功能，该功能用于校正光刻掩模布局。
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公开(公告)号：US20140053117A1
公开(公告)日：2014-02-20
申请号：US13997565
申请日：2011-12-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F17/5068
摘要： Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
摘要翻译： 提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。 一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。 可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。
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6.发明申请Measurement of a scattered light point spread function (PSF) for microelectronic photolithography 失效用于微电子光刻的散射光点扩散函数（PSF）的测量公开(公告)号：US20080020292A1
公开(公告)日：2008-01-24
申请号：US11490924
申请日：2006-07-21
CPC分类号： G03F7/70941 , G03F1/44 , G03F7/70591
摘要： A scattered light point spread function is measured for use in fabricating microelectronic and micromechanical devices using photolithography. In one example, a photosensitive layer of a microelectronic substrate is exposed through a test mask, the test mask having a series of differently sized patterns, each pattern surrounding a central monitor feature, the differently sized patterns each being evenly distributed about its respective central monitor feature. An indication of the exposure of the photosensitive layer is measured for a plurality of the series of differently sized patterns. The exposure indication is compared to the pattern size. The comparison is fitted to a function and the function is applied in correcting photolithography mask layouts.
摘要翻译： 测量散射光点扩散函数用于使用光刻制造微电子和微机械器件。 在一个示例中，微电子衬底的感光层通过测试掩模曝光，测试掩模具有一系列不同大小的图案，每个图案围绕中央监视器特征，不同尺寸的图案均分布在其相应的中央监视器周围 特征。 测量多个不同尺寸图案的一系列感光层的曝光指示。 将曝光指示与图案尺寸进行比较。 该比较适用于功能，该功能用于校正光刻掩模布局。
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公开(公告)号：US07254803B2
公开(公告)日：2007-08-07
申请号：US10955748
申请日：2004-09-30
申请人： Seongtae Jeong , Yan Borodovsky
发明人： Seongtae Jeong , Yan Borodovsky
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.
摘要翻译： 用于生成测试结构的系统和技术。 测试结构可以符合集成电路设计的一部分的一组设计规则。 测试结构可以包括可能在富集环境中的基本图形。 例如，测试结构可以包括一个或多个附加图形，例如周围图形，外部图形和/或对称图形。 可以使用多个测试结构来检查用于校正布局的校正算法。
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公开(公告)号：US20170018499A1
公开(公告)日：2017-01-19
申请号：US15124867
申请日：2014-05-08
IPC分类号： H01L23/525 , H01L23/528 , H01L21/768
CPC分类号： H01L23/5256 , H01L21/76816 , H01L21/76877 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.
摘要翻译： 互连保险丝结构，包括带有颈缩线段的保险丝，以及制造这种结构的方法。 由施加的保险丝编程电压驱动的电流可以打开颈部熔断器段以影响IC的工作。 在实施例中，熔丝结构包括与中心互连线等距的一对相邻的互连线。 在另外的实施例中，中心互连线以及相邻互连线中的至少一个包括横向宽度的线段，其相差相同且互补。 在另外的实施例中，中心互连线在颈缩线段的相对端互连。 在进一步的实施例中，颈缩线段由间距减小的基于间隔物的图案化工艺制成。
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公开(公告)号：US20060075366A1
公开(公告)日：2006-04-06
申请号：US10955748
申请日：2004-09-30
申请人： Seongtae Jeong , Yan Borodovsky
发明人： Seongtae Jeong , Yan Borodovsky
CPC分类号： G06F17/5081
摘要： Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.
摘要翻译： 用于生成测试结构的系统和技术。 测试结构可以符合集成电路设计的一部分的一组设计规则。 测试结构可以包括可能在富集环境中的基本图形。 例如，测试结构可以包括一个或多个附加图形，例如周围图形，外部图形和/或对称图形。 可以使用多个测试结构来检查用于校正布局的校正算法。
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公开(公告)号：US08959465B2
公开(公告)日：2015-02-17
申请号：US13997565
申请日：2011-12-30
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F17/5068
摘要： Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
摘要翻译： 提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。 一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。 可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。
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