公开(公告)号：US06894925B1

公开(公告)日：2005-05-17

申请号：US10342585

申请日：2003-01-14

申请人： Sheunghee Park ,  Sameer S. Haddad ,  Chi Chang ,  Richard M. Fastow ,  Ming Sang Kwan ,  Zhigang Wang

发明人： Sheunghee Park ,  Sameer S. Haddad ,  Chi Chang ,  Richard M. Fastow ,  Ming Sang Kwan ,  Zhigang Wang

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

CPC分类号： G11C11/5621 ,  G11C16/0416 ,  H01L29/42324 ,  H01L29/7883

摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.

摘要翻译： 提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。 可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。 本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。 偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。 偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。 一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

公开(公告)号：US06469939B1

公开(公告)日：2002-10-22

申请号：US09969572

申请日：2001-10-01

申请人： Zhigang Wang ,  Richard Fastow ,  Sheung-Hee Park ,  Sameer S. Haddad ,  Chi Chang

发明人： Zhigang Wang ,  Richard Fastow ,  Sheung-Hee Park ,  Sameer S. Haddad ,  Chi Chang

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404

摘要： A source resistor or a positive voltage is coupled to the source and a negative bias voltage is applied at the substrate or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected.

摘要翻译： 源极电阻或正电压耦合到源极，并且在闪存单元的衬底或p阱处施加负偏置电压，以在编程期间和/或在APDE（擦除后自动程序干扰）处理期间提高效率 闪存设备。 此外，在用于对闪速存储器件进行编程的系统和方法中，选择多个闪速存储器单元的阵列中的闪存单元进行编程。 控制栅极编程电压被施加到所选择的闪速存储器单元的控制栅极，并且位线编程电压通过公共位线端子被施加到所选择的闪存单元的漏极，所述公共位线端子选择闪存的漏极 单元格已连接。

公开(公告)号：US06510085B1

公开(公告)日：2003-01-21

申请号：US09861031

申请日：2001-05-18

申请人： Richard Fastow ,  Sheunghee Park ,  Zhigang Wang ,  Sameer Haddad ,  Chi Chang

发明人： Richard Fastow ,  Sheunghee Park ,  Zhigang Wang ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404

摘要： Methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during both programming and soft programming while maintaining fast programming speeds. During programming, a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts; is applied to the drain, a voltage of between 0.5 and 2.0 volts is applied to the source and a voltage of between minus 2 and minus 0.5 volts is applied to the substrate of the selected cell to be programmed. During soft programming, a voltage of between 0.5 and 4.5 volts is applied to the control gates, between 4 and 5.5 volts is applied to the drains, between 0.5 and 2 volts is applied to the sources and between minus 2.0 and minus 0.5 volts is applied to the substrates of the memory cells.

摘要翻译： 编程和软编程短节目NOR闪存单元的方法，可在编程和软编程期间减少编程电流和列泄漏，同时保持快速的编程速度。 在编程期间，7至10伏之间的电压施加到控制栅极，电压在4和6伏之间; 施加到漏极，将0.5至2.0伏之间的电压施加到源极，并且在所述要编程的所选择的单元的衬底之间施加负2和负0.5伏之间的电压。 在软编程期间，向控制栅极施加0.5至4.5伏之间的电压，在漏极之间施加4至5.5伏之间的电压，施加0.5至2伏之间的电压，并施加负2.0至负0.5伏之间 到存储单元的基板。

公开(公告)号：US07414281B1

公开(公告)日：2008-08-19

申请号：US10658936

申请日：2003-09-09

申请人： Richard M. Fastow ,  Yue-Song He ,  Zhigang Wang

发明人： Richard M. Fastow ,  Yue-Song He ,  Zhigang Wang

IPC分类号： H01L29/76

CPC分类号： H01L29/513 ,  H01L29/7881

摘要： A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.

摘要翻译： 描述闪存单元及其形成方法。 闪速存储单元可以包括在衬底和栅极元件之间具有源极和漏极的衬底，栅极元件和介电层。 电介质层包括介电常数大于二氧化硅的电介质材料。

公开(公告)号：US09585550B2

公开(公告)日：2017-03-07

申请号：US10561649

申请日：2004-06-24

申请人： Eric Abel ,  James R. Hewit ,  Alan P. Slade ,  Zhigang Wang

发明人： Eric Abel ,  James R. Hewit ,  Alan P. Slade ,  Zhigang Wang

IPC分类号： A61M29/00 ,  A61B1/32 ,  A61B1/31

CPC分类号： A61B1/32 ,  A61B1/31 ,  A61M29/00

摘要： There is disclosed medical apparatus of the type for use in surgery such as transanal endoscopic microsurgery, as well as methods of providing access to, inspecting and enabling surgery within a body passage. In one embodiment of the invention, medical apparatus in the form of a rectal expander (10) is disclosed, the expander (10) being adapted for location at least partly within a body passage such as the rectum (12) of a patient (14), the expander (10) having a leading end (18) and an access area in the form of an opening (20) for access from the expander (10) into the rectum (12), at least part of the opening (20) being spaced from the leading end (18), and the expander (10) being controllably movable between collapse and expansion positions, for expanding the rectum (12).

摘要翻译： 公开了用于外科手术的类型的医疗装置，例如经肛门内窥镜显微外科手术，以及提供身体通道内的进入，检查和使手术的方法。 在本发明的一个实施例中，公开了直肠扩张器（10）形式的医疗装置，所述扩张器（10）适于至少部分位于身体通道内，例如患者（14）的直肠（12） ），所述膨胀器（10）具有前端（18）和开口（20）形式的进入区域，用于从所述膨胀器（10）进入直肠（12），所述开口（20）的至少一部分 ）与所述前端（18）间隔开，并且所述膨胀器（10）可控制地在塌缩和膨胀位置之间移动，用于扩张直肠（12）。

公开(公告)号：US08864645B2

公开(公告)日：2014-10-21

申请号：US11795137

申请日：2006-01-13

申请人： Eric William Abel ,  Zhigang Wang

发明人： Eric William Abel ,  Zhigang Wang

IPC分类号： H04R25/02

CPC分类号： H04R25/606 ,  A61F2002/183 ,  H04R17/02

摘要： The present invention concerns an actuator for an implantable hearing aid for implantation into the human middle ear. The actuator comprises a substantially elongate piezoelectric component (34, 36) having first and second operating end faces (41, 43), said end faces extending substantially at right angles to the longitudinal axis of the piezoelectric component. Also there is provided a frame component comprising at least one flextensional amplifier element (32), the flextensional amplifier element being integral with and connecting first and second frame end portions (42, 44), the first and second frame end portions also extending substantially at right angles to longitudinal axis of the piezoelectric component when fitted thereto, whereby the first and second end portions are in contact with the piezoelectric component end faces.

摘要翻译： 本发明涉及用于植入人中耳的可植入助听器的致动器。 致动器包括具有第一和第二操作端面（41,43）的基本上细长的压电元件（34,36），所述端面基本上与压电元件的纵向轴线成直角延伸。 还提供了一种包括至少一个张力放大器元件（32）的框架部件，该屈曲放大器元件与第一和第二框架端部（42,44）成一体并且连接第一和第二框架端部（42,44），第一和第二框架端部也基本上延伸 与压电部件的纵轴成直角，由此第一和第二端部与压电元件端面接触。

公开(公告)号：US08742175B2

公开(公告)日：2014-06-03

申请号：US13695600

申请日：2011-11-04

申请人： Yongbo Zhang ,  Yanchao Wang ,  Yapeng Wang ,  Huaihai Song ,  Zhigang Wang

发明人： Yongbo Zhang ,  Yanchao Wang ,  Yapeng Wang ,  Huaihai Song ,  Zhigang Wang

IPC分类号： C07C49/00 ,  C07C45/00 ,  C07C211/00 ,  C07C217/00 ,  C07C261/00

CPC分类号： C08F2/50 ,  C07C49/784 ,  C07C49/83 ,  C07C49/84 ,  C07C59/90 ,  C07C62/38 ,  C07C69/16 ,  C07C69/18 ,  C07C69/30 ,  C07C69/54 ,  C07C69/75 ,  C07C69/757 ,  C07C69/82 ,  C07C225/16 ,  C07C229/60 ,  C07C323/22 ,  C07C2601/14 ,  C07D207/404 ,  C07D209/48 ,  C07D251/30 ,  C07F7/1804 ,  C08F2/48

摘要： The present invention discloses novel aromatic ketone compounds with functional substitution groups at para- or meta positions which can be used as photo-initiators or effective components of photo-initiator mixtures for the photopolymerizations of ethylenically unsaturated systems. The preparation of these compounds is also disclosed.

摘要翻译： 本发明公开了具有在对位或间位具有官能取代基的新型芳族酮化合物，其可用作光引发剂或光引发剂混合物的有效成分，用于烯属不饱和体系的光聚合。 还公开了这些化合物的制备。

公开(公告)号：US07851306B2

公开(公告)日：2010-12-14

申请号：US12327641

申请日：2008-12-03

申请人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

发明人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

摘要翻译： 本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。 阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。 在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。 植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。 源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。 源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。 与漏极触点排共线的源触点的布置允许直线字线形成。

公开(公告)号：US20100296225A1

公开(公告)日：2010-11-25

申请号：US12626562

申请日：2009-11-25

申请人： Patrick Smith ,  Zhigang Wang

发明人： Patrick Smith ,  Zhigang Wang

IPC分类号： H01G4/06 ,  H01G7/00

CPC分类号： H01L27/016 ,  G08B13/2437 ,  H01L27/0207 ,  H01L27/0808 ,  H01L28/60 ,  H01L28/88 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49016

摘要： The present invention relates to tunable capacitors, devices including tunable capacitors, and methods of making and using tunable capacitors and devices. One or more secondary tunable capacitors can be connected to a primary capacitor by printing a connector conducting layer or feature to obtain a desired net capacitance. Digitally printing the connector conducting layer allows the number of secondary capacitors connected into the circuit to be determined during the integrated circuit fabrication process, without the need for individual masks connecting the appropriate number of secondary capacitors. This provides an in-process or post-process trimming method to obtain the desired precision and accuracy for capacitors. Various sizes and combinations of secondary capacitors can be connected to obtain high precision capacitors and/or improved matching of capacitance values.

摘要翻译： 本发明涉及可调电容器，包括可调电容器的器件，以及制造和使用可调电容器和器件的方法。 可以通过印刷连接器导电层或特征来将一个或多个二次可调谐电容器连接到主电容器，以获得期望的净电容。 数字印刷连接器导电层允许在集成电路制造过程中确定连接到电路中的次级电容器的数量，而不需要连接适当数量的次级电容器的单独的掩模。 这提供了一种过程中或后处理修剪方法，以获得电容器所需的精度和精度。 可以连接各种尺寸和二次电容器的组合以获得高精度电容器和/或改善电容值的匹配。

公开(公告)号：US20100295661A1

公开(公告)日：2010-11-25

申请号：US12625435

申请日：2009-11-24

申请人： Vivek SUBRAMANIAN ,  Mingming Mao ,  Zhigang Wang

发明人： Vivek SUBRAMANIAN ,  Mingming Mao ,  Zhigang Wang

IPC分类号： H04B7/24 ,  H04B1/04 ,  H03K3/36 ,  H03B5/12

CPC分类号： H04B1/04 ,  G06K7/0008 ,  G06K7/10059 ,  G06K19/0723 ,  H01L22/20 ,  H01L2924/0002 ,  H03B5/1203 ,  H03K3/0315 ,  H03K3/033 ,  H03K3/355 ,  H03K5/13 ,  H03K5/133 ,  H04H20/16 ,  H01L2924/00

摘要： Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.

摘要翻译： 被配置为产生随机延迟的电路和电路元件，单稳态振荡器，被配置为广播重复消息无线系统的电路，以及用于形成这种电路，装置和系统的方法。 本发明有利地提供了在无线电子应用中特别是RFID应用中基于TFT技术的相对较低成本的延迟产生电路。 这种新颖的，技术上简化的，低成本的基于TFT的延迟产生电路实现了新颖的无线电路，设备和系统以及用于生产这样的电路，设备和系统的方法。