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    Image synthesizing apparatus for superposing a second image on a first image
    3.
    发明授权
    Image synthesizing apparatus for superposing a second image on a first image 失效
    用于将第二图像叠加在第一图像上的图像合成装置

    公开(公告)号：US5179642A

    公开(公告)日：1993-01-12

    申请号：US856827

    申请日：1992-03-25

    申请人： Shigeru Komatsu

    发明人： Shigeru Komatsu

    IPC分类号： G06T15/40

    CPC分类号： G06T15/40

    摘要： An image synthesizing apparatus for synthesizing first and second images with each other which includes a first display memory for storing a first image data constituting a first image, and a display memory control device for comparing a second image data for constituting a second image with a predetermined image data to thereby judge whether the second image data is to be written into the first display memory or not.

    摘要翻译： 一种用于合成第一和第二图像的图像合成装置，包括：第一显示存储器，用于存储构成第一图像的第一图像数据;以及显示存储器控制装置，用于将用于构成第二图像的第二图像数据与预定的 从而判断第二图像数据是否被写入第一显示存储器。

    Frame buffer memory for display
    4.
    发明授权
    Frame buffer memory for display 失效
    帧缓冲存储器用于显示

    公开(公告)号：US4980765A

    公开(公告)日：1990-12-25

    申请号：US464214

    申请日：1990-01-12

    申请人： Yoshimichi Kudo ,  Shigeru Komatsu

    发明人： Yoshimichi Kudo ,  Shigeru Komatsu

    IPC分类号： G09G5/00 ,  G06F12/02 ,  G06T1/60 ,  G09G5/14 ,  G09G5/34 ,  G09G5/39 ,  G09G5/397

    CPC分类号： G09G5/14 ,  G09G5/397 ,  G09G2360/126

    摘要： A frame buffer memory capable of storing video data for plural frames of pictures with memory areas irrelevant to the display being reduced to a minimum, which video data consist of a number of pixels unequal to a power of "2" in the vertical and horizontal directions, respectively. The frame buffer memory is realized by using multi-port video RAMs and includes a plurality of regions for display and auxiliary regions. The regions for display includes at least first and second display regions which partially overlap each other. The auxiliary regions store the video data contained in the overlapping portion (overlapping region) of the first and second display regions, the video data stored in the auxiliary region being transferred to the overlapping region as occasion requires.

    摘要翻译： 能够将与图像无关的存储区域的多帧图像的视频数据的帧缓冲存储器减少到最小，哪个视频数据由不同于垂直和水平方向上的“2”的功率的像素数组成 ， 分别。 帧缓冲存储器是通过使用多端口视频RAM来实现的，并且包括用于显示和辅助区域的多个区域。 用于显示的区域至少包括彼此部分重叠的至少第一和第二显示区域。 辅助区域存储包含在第一和第二显示区域的重叠部分（重叠区域）中的视频数据，根据需要，存储在辅助区域中的视频数据被传送到重叠区域。

    Trimming of metal interconnection layer by selective migration of metal atoms by energy beams
    5.
    发明授权
    Trimming of metal interconnection layer by selective migration of metal atoms by energy beams 失效
    通过能量束选择性迁移金属原子来修剪金属互连层

    公开(公告)号：US4692190A

    公开(公告)日：1987-09-08

    申请号：US813039

    申请日：1985-12-24

    申请人： Shigeru Komatsu

    发明人： Shigeru Komatsu

    IPC分类号： H01L21/3205 ,  H01L21/268 ,  H01L21/82 ,  H01L23/525 ,  H01C7/00 ,  B23K26/00

    CPC分类号： H01L23/525 ,  H01L21/268 ,  H01L2924/0002 ,  Y10S148/093 ,  Y10S148/14

    摘要： Semiconductor body is prepared and a film is formed on the semiconductor body, followed by forming an interconnection layer of aluminum alloy on the insulating film. A silicon oxide film is formed on the interconnection layer, followed by removing that portion of the silicon oxide film which is situated on a predetermined trimming area of the interconnection layer. A silicon nitride film is formed on the whole surface of the resultant structure. An energy beam is directed onto the predetermined trimming area of the interconnection layer, causing the interconnection layer to be locally heated to 400.degree. to 600.degree. C. whereby atoms in the interconnection layer migrate to permit the interconnection layer to be trimmed.

    摘要翻译： 制备半导体体，在半导体体上形成膜，然后在绝缘膜上形成铝合金的配线层。 在互连层上形成氧化硅膜，然后除去位于互连层的预定修整区域上的部分氧化硅膜。 在所得结构的整个表面上形成氮化硅膜。 能量束被引导到互连层的预定修整区域上，使得互连层局部加热至400℃至600℃，由此互连层中的原子迁移以允许互连层被修整。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4484212A

    公开(公告)日：1984-11-20

    申请号：US335712

    申请日：1981-12-29

    申请人： Shigeru Komatsu ,  Michio Nakamura ,  Katsuji Fujita

    发明人： Shigeru Komatsu ,  Michio Nakamura ,  Katsuji Fujita

    IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/08 ,  H01L29/84 ,  H01L23/48 ,  H01L27/02 ,  H01L29/44

    CPC分类号： H01L23/585 ,  H01L23/522 ,  H01L27/0802 ,  H01L2924/0002 ,  Y10S257/925 ,  Y10S73/04

    摘要： A semiconductor device comprising a semiconductor substrate having at least two resistor elements, wherein said resistor elements have a specific resistance ratio relative to each other, an insulation layer formed on a major surface of said semiconductor substrate, a circuit wiring layer formed on said insulation layer covering a portion of said insulation layer which corresponds to at least one of said resistor elements, and a dummy wiring layer made of the same material as that of the circuit wiring layer and formed on the insulation layer covering that portion of said insulation layer which corresponds to the resistor element or elements not covered by said circuit wiring layer, and where the ratio of an overlapping area of one resistor element in said circuit wiring layer and an overlapping area of the other resistor element and said dummy wiring layer is equal to a resistance ratio of said resistor elements.

    摘要翻译： 一种半导体器件，包括具有至少两个电阻元件的半导体衬底，其中所述电阻元件相对于彼此具有比电阻比，形成在所述半导体衬底的主表面上的绝缘层，形成在所述绝缘层上的电路布线层 覆盖对应于所述电阻元件中的至少一个的所述绝缘层的一部分，以及由与所述电路布线层相同的材料制成的虚拟布线层，并形成在所述绝缘层上，覆盖所述绝缘层对应的部分 连接到所述电路布线层未被覆盖的电阻元件或元件，并且其中所述电路布线层中的一个电阻元件的重叠区域与所述另一个电阻元件与所述伪布线层的重叠区域的重叠面积之比等于电阻 所述电阻元件的比例。

    Polysilicon emitter and base contacts separated by lightly doped poly separator
    7.
    发明授权
    Polysilicon emitter and base contacts separated by lightly doped poly separator 失效
    多晶硅发射极和基极触点由轻掺杂的多分离器分离

    公开(公告)号：US4451844A

    公开(公告)日：1984-05-29

    申请号：US289961

    申请日：1981-08-04

    申请人： Shigeru Komatsu ,  Michio Nakamura

    发明人： Shigeru Komatsu ,  Michio Nakamura

    IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L27/06 ,  H01L29/417 ,  H01L29/45 ,  H01L23/50 ,  H01L23/52

    CPC分类号： H01L21/28525 ,  H01L27/06 ,  H01L29/417 ,  H01L29/456

    摘要： A semiconductor device comprising a semiconductor substrate of an N conductivity type; an insulation layer of a predetermined pattern for selectively covering the substrate; a first region of a P conductivity type formed in that area of the substrate which is surrounded by the insulation layer; a second region of the P.sup.+ conductivity type having a high impurity concentration and formed in the first region; a third region of the N conductivity type formed in the first region; a polycrystalline silicon layer formed on the major surface of the substrate, said polycrystalline silicon layer comprising a first portion of the P conductivity type contacting the second region, a second portion of the N conductivity type contacting the third region and a third portion contacting the first region, said first and second portions constituting first and second contacting electrodes, respectively, and the third portion having a predetermined impurity concentration and constituting a separation portion for insulating the first and second portions from each other.

    摘要翻译： 一种半导体器件，包括N导电类型的半导体衬底; 用于选择性地覆盖衬底的预定图案的绝缘层; 形成在由绝缘层包围的基板的该区域中的P导电型的第一区域; 形成在第一区域中的具有高杂质浓度的P +导电型的第二区域; 形成在第一区域中的N导电类型的第三区域; 形成在所述基板的主表面上的多晶硅层，所述多晶硅层包括接触所述第二区域的P导电类型的第一部分，与所述第三区域接触的所述N导电类型的第二部分和接触所述第一区域的第三部分 所述第一和第二部分分别构成第一和第二接触电极，第三部分具有预定的杂质浓度，并构成用于使第一和第二部分彼此绝缘的分离部分。

    Memory selecting system
    8.
    发明授权
    Memory selecting system 失效
    内存选择系统

    公开(公告)号：US4388707A

    公开(公告)日：1983-06-14

    申请号：US279071

    申请日：1981-06-30

    申请人： Shigeru Komatsu ,  Kazushi Mizukami ,  Tsuguji Tachiuchi ,  Kunihiko Nagai ,  Takuo Koyama

    发明人： Shigeru Komatsu ,  Kazushi Mizukami ,  Tsuguji Tachiuchi ,  Kunihiko Nagai ,  Takuo Koyama

    IPC分类号： G06F12/00 ,  G06F12/06 ,  G11C8/12 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G06F12/0623

    摘要： A memory selection system which facilitates the addition of an external memory to a digital processing unit having an internal memory is disclosed. When a plurality of memories have the same addresses and an overlapped address is accessed, priority among the memories having the overlapped address is discriminated to enable only the memory having the highest priority (last attached memory) to be selected for access and to disable the access of the other memories.

    摘要翻译： 公开了一种便于将外部存储器添加到具有内部存储器的数字处理单元的存储器选择系统。 当多个存储器具有相同的地址并且重叠地址被访问时，区分具有重叠地址的存储器中的优先级，以使得仅能够选择具有最高优先级的存储器（最后附加存储器）以进行访问并禁用访问 的其他记忆。

    Method for designing a manufacturing process, method for providing manufacturing process design and technology computer-aided design system
    10.
    发明申请
    Method for designing a manufacturing process, method for providing manufacturing process design and technology computer-aided design system 失效
    设计制造过程的方法，提供制造工艺设计和技术计算机辅助设计系统的方法

    公开(公告)号：US20050113951A1

    公开(公告)日：2005-05-26

    申请号：US10933439

    申请日：2004-09-03

    申请人： Tatsuo Akiyama ,  Masahiro Abe ,  Kenji Hirakawa ,  Shigeru Komatsu

    发明人： Tatsuo Akiyama ,  Masahiro Abe ,  Kenji Hirakawa ,  Shigeru Komatsu

    IPC分类号： H01L21/02 ,  G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/5068

    摘要： A method for designing a manufacturing process of an electronic device includes calibrating a technology computer-aided design system by fitting simulation parameters of manufacturing process and electrical characteristic simulations, using first feature of commercial manufacturing process of first electronic device manufactured by first manufacturing facilities, and first electrical characteristic of the first electronic device; acquiring second feature of trial manufacturing process of second electronic device manufactured by second manufacturing facilities, and second electrical characteristic of the second electronic device; calculating simulation electrical characteristic of the second electronic device by substituting the second feature to the manufacturing process simulation corresponding to the trial manufacturing process; comparing the second electrical characteristic with the simulation electrical characteristic; and creating design specification of commercial manufacturing process of the second manufacturing facilities based on difference between the second electrical characteristic and the simulation electrical characteristic.

    摘要翻译： 一种设计电子设备的制造方法的方法，包括使用第一制造设备制造的第一电子设备的商业制造工艺的第一特征，通过拟合制造工艺和电气特性模拟的仿真参数来校准技术计算机辅助设计系统，以及 第一电子装置的第一电特性; 获得由第二制造设备制造的第二电子装置的试制制造过程的第二特征和第二电子装置的第二电特性; 通过将第二特征代入对应于试制造过程的制造过程模拟来计算第二电子装置的模拟电特性; 将第二电特性与仿真电特性进行比较; 并基于第二电特性和仿真电特性之间的差异，创建第二制造设备的商业制造过程的设计规范。