公开(公告)号：US20130193531A1

公开(公告)日：2013-08-01

申请号：US13712062

申请日：2012-12-12

申请人： FUJI ELECTRIC CO., LTD.

发明人： Mutsuo NISHIKAWA ,  Kazunori SAITO

IPC分类号： H01L29/84

CPC分类号： H01L29/84 ,  G01L9/0042 ,  G01L9/0045 ,  G01L9/0048 ,  G01P15/123 ,  G01P2015/084 ,  H01L29/0649 ,  Y10S257/925

摘要： Provided by some aspects of the invention is a relatively low-cost, relatively highly accurate physical quantity sensor, and a manufacturing method thereof, that relaxes thermal stress from an outer peripheral portion of a diaphragm in a silicon-on-nothing (“SON”) structure. By providing a stress relaxation region (trench groove) in an outer peripheral portion of a diaphragm in a SON structure, there can be, in some aspects of the invention, a benefit of relaxing the transmission to the diaphragm of thermal stress generated by the difference in linear expansion coefficient between a package and chip, and it is possible to relax the transmission to an electronic circuit disposed in an outer peripheral portion of mechanical stress generated by a measured pressure. As a result of this, it is possible to provide a highly accurate physical quantity sensor.

摘要翻译： 通过本发明的某些方面提供了一种相对低成本，相对高度精确的物理量传感器及其制造方法，其在无硅无极（“SON”）中松弛来自隔膜的外周部分的热应力， ） 结构体。 通过在SON结构中的隔膜的外周部设置应力松弛区域（沟槽），在本发明的一些方面，可以有利于放松由隔膜产生的热应力对隔膜的传递 在封装和芯片之间的线膨胀系数，并且可以放松到设置在由测量压力产生的机械应力的外周部分中的电子电路的传输。 作为其结果，可以提供高精度的物理量传感器。

公开(公告)号：US5929519A

公开(公告)日：1999-07-27

申请号：US979778

申请日：1997-11-26

申请人： Mutsuhiro Mori ,  Ryuichi Saito ,  Shin Kimura ,  Syuuji Saitoo ,  Kiyoshi Nakata ,  Akira Horie ,  Yoshihiko Koike ,  Shigeki Sekine

发明人： Mutsuhiro Mori ,  Ryuichi Saito ,  Shin Kimura ,  Syuuji Saitoo ,  Kiyoshi Nakata ,  Akira Horie ,  Yoshihiko Koike ,  Shigeki Sekine

IPC分类号： H01L23/04 ,  H01L23/24 ,  H01L25/07 ,  H02M7/00 ,  H02M7/48 ,  H02M7/487 ,  H03K17/0814 ,  H01L23/34

CPC分类号： H02M7/487 ,  H01L23/04 ,  H01L23/24 ,  H01L24/49 ,  H01L25/072 ,  H02M7/003 ,  H03K17/08148 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01055 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10S257/925

摘要： An inverter device includes plural modules, each module being formed by a series circuit having a parallel circuit of a switching device and a first diode, and a parallel circuit of a second switching device and a second diode, allowing a reduced size, high reliability, high frequency switching and low noise. Each of the semiconductor modules includes a plurality of switching device chips and at least one diode chip formed on a metal substrate. Electrode plates are provided in locations of the module adjacent to the switching device chips and the diode chips to facilitate connection of the electrodes of the respective chips to one another and to the outside of the module.

摘要翻译： 逆变器装置包括多个模块，每个模块由具有开关装置和第一二极管的并联电路的串联电路以及第二开关装置和第二二极管的并联电路形成，允许减小尺寸，高可靠性， 高频开关和低噪声。 每个半导体模块包括多个开关器件芯片和形成在金属衬底上的至少一个二极管芯片。 电极板设置在与开关器件芯片和二极管芯片相邻的模块的位置处，以便于将各个芯片的电极彼此连接并连接到模块的外部。

公开(公告)号：US5418174A

公开(公告)日：1995-05-23

申请号：US905020

申请日：1992-06-26

申请人： Alexander Kalnitsky

发明人： Alexander Kalnitsky

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/266

CPC分类号： H01L21/28185 ,  H01L21/28176 ,  H01L21/3105 ,  H01L21/823462 ,  H01L29/51 ,  Y10S257/906 ,  Y10S257/921 ,  Y10S257/925 ,  Y10S438/953

摘要： A method is provided for forming a radiation hard dielectric region of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide region, a gate oxide layer and an interlevel dielectric layer are formed over the integrated circuit. Silicon ions are implanted separately into the field oxide region, gate oxide layer and interlevel dielectric layer to a sufficient dosage of less than or equal to approximately 1.times.10.sup.14 /cm.sup.2 to form electron traps to capture radiation induced electrons. This method allows for selective enhancement of radiation hardness of a portion of a circuit, thus providing an on-chip "dosimeter" which can be used to compensate the circuit for the loss of performance due to ionizing radiation.

摘要翻译： 提供一种用于形成半导体集成电路的辐射硬介电区域的方法和根据该集成电路形成的集成电路。 在集成电路上形成场氧化物区域，栅极氧化物层和层间电介质层。 将硅离子分别注入到场氧化物区域，栅极氧化物层和层间电介质层中，以足够的剂量小于或等于约1×10 14 / cm 2，以形成捕获辐射诱导电子的电子阱。 该方法允许选择性地增强电路的一部分的辐射硬度，从而提供片上“剂量计”，其可用于补偿电路由于电离辐射导致的性能损失。

公开(公告)号：US4731642A

公开(公告)日：1988-03-15

申请号：US704572

申请日：1985-02-22

申请人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

发明人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L23/50 ,  H01L23/54 ,  H01L29/44

CPC分类号： H01L23/522 ,  G11C5/025 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/922 ,  Y10S257/925 ,  Y10S438/926

摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.

摘要翻译： 一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。 布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。 布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

公开(公告)号：US4484212A

公开(公告)日：1984-11-20

申请号：US335712

申请日：1981-12-29

申请人： Shigeru Komatsu ,  Michio Nakamura ,  Katsuji Fujita

发明人： Shigeru Komatsu ,  Michio Nakamura ,  Katsuji Fujita

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/08 ,  H01L29/84 ,  H01L23/48 ,  H01L27/02 ,  H01L29/44

CPC分类号： H01L23/585 ,  H01L23/522 ,  H01L27/0802 ,  H01L2924/0002 ,  Y10S257/925 ,  Y10S73/04

摘要： A semiconductor device comprising a semiconductor substrate having at least two resistor elements, wherein said resistor elements have a specific resistance ratio relative to each other, an insulation layer formed on a major surface of said semiconductor substrate, a circuit wiring layer formed on said insulation layer covering a portion of said insulation layer which corresponds to at least one of said resistor elements, and a dummy wiring layer made of the same material as that of the circuit wiring layer and formed on the insulation layer covering that portion of said insulation layer which corresponds to the resistor element or elements not covered by said circuit wiring layer, and where the ratio of an overlapping area of one resistor element in said circuit wiring layer and an overlapping area of the other resistor element and said dummy wiring layer is equal to a resistance ratio of said resistor elements.

摘要翻译： 一种半导体器件，包括具有至少两个电阻元件的半导体衬底，其中所述电阻元件相对于彼此具有比电阻比，形成在所述半导体衬底的主表面上的绝缘层，形成在所述绝缘层上的电路布线层 覆盖对应于所述电阻元件中的至少一个的所述绝缘层的一部分，以及由与所述电路布线层相同的材料制成的虚拟布线层，并形成在所述绝缘层上，覆盖所述绝缘层对应的部分 连接到所述电路布线层未被覆盖的电阻元件或元件，并且其中所述电路布线层中的一个电阻元件的重叠区域与所述另一个电阻元件与所述伪布线层的重叠区域的重叠面积之比等于电阻 所述电阻元件的比例。

公开(公告)号：US3666995A

公开(公告)日：1972-05-30

申请号：US3666995D

申请日：1970-04-28

申请人： PHILIPS CORP

发明人： WENSINK BERNARDUS LEONARDUS ,  CENSE ADRIAAN

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/08 ,  H01L19/00

CPC分类号： H01L27/0802 ,  Y10S257/925

摘要： In an integrated semiconductor device according to the invention, a resistance element with small resistance comprises between its electric connections a number of parallel arranged resistance zones of the same width and thickness. The influence of inaccuracies in providing the electric connections is eliminated, and a zone of a resistance element with large resistor may have the same width and thickness as the parallel zones of the resistance element with small resistance.

摘要翻译： 在根据本发明的集成半导体器件中，具有小电阻的电阻元件在其电连接之间包括相同宽度和厚度的多个平行布置的电阻区域。 消除了提供电连接的不精确度的影响，并且具有大电阻器的电阻元件的区域可以具有与电阻小的电阻元件的平行区域相同的宽度和厚度。

公开(公告)号：US3570112A

公开(公告)日：1971-03-16

申请号：US3570112D

申请日：1967-12-01

申请人： NAT DEFENCE CANADA

发明人： BARRY ALBERT L ,  PAGE DONALD F

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L29/00 ,  H01L29/76 ,  B01J17/00 ,  H01G13/00

CPC分类号： H01L29/00 ,  H01L21/00 ,  H01L21/30 ,  H01L29/76 ,  Y10S257/925 ,  Y10S438/953

摘要： A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT DEVICE IS RENDERED LESS SENSITIVE TO IONIZING RADIATION BY SUBJECTING THE DEVICE TO IONIZING RADIATION AT A POSITIVE GATE BIAS SEVERAL TIMES LARGER THAN THE NORMAL OPERATING BIAS VOLTAGE OF THE DEVICE, AND THEN PARTIALLY TEMPERATURE ANNEALING THE DEVICE.

公开(公告)号：US08884385B2

公开(公告)日：2014-11-11

申请号：US13712062

申请日：2012-12-12

申请人： Fuji Electric Co., Ltd.

发明人： Mutsuo Nishikawa ,  Kazunori Saito

IPC分类号： G01L9/00 ,  H01L29/84 ,  H01L29/06 ,  G01P15/12 ,  G01P15/08

CPC分类号： H01L29/84 ,  G01L9/0042 ,  G01L9/0045 ,  G01L9/0048 ,  G01P15/123 ,  G01P2015/084 ,  H01L29/0649 ,  Y10S257/925

摘要： Provided by some aspects of the invention is a relatively low-cost, relatively highly accurate physical quantity sensor, and a manufacturing method thereof, that relaxes thermal stress from an outer peripheral portion of a diaphragm in a silicon-on-nothing (“SON”) structure. By providing a stress relaxation region (trench groove) in an outer peripheral portion of a diaphragm in a SON structure, there can be, in some aspects of the invention, a benefit of relaxing the transmission to the diaphragm of thermal stress generated by the difference in linear expansion coefficient between a package and chip, and it is possible to relax the transmission to an electronic circuit disposed in an outer peripheral portion of mechanical stress generated by a measured pressure. As a result of this, it is possible to provide a highly accurate physical quantity sensor.

摘要翻译： 通过本发明的某些方面提供了一种相对低成本，相对高度精确的物理量传感器及其制造方法，其在无硅无极（“SON”）中松弛来自隔膜的外周部分的热应力， ） 结构体。 通过在SON结构中的隔膜的外周部设置应力松弛区域（沟槽），在本发明的一些方面，可以有利于放松由隔膜产生的热应力对隔膜的传递 在封装和芯片之间的线膨胀系数，并且可以放松到设置在由测量压力产生的机械应力的外周部分中的电子电路的传输。 作为其结果，可以提供高精度的物理量传感器。

公开(公告)号：US5821618A

公开(公告)日：1998-10-13

申请号：US514771

申请日：1995-08-14

申请人： Alfons Graf ,  Peter Huber ,  Xaver Schloegel ,  Peter Sommer

发明人： Alfons Graf ,  Peter Huber ,  Xaver Schloegel ,  Peter Sommer

IPC分类号： H01L23/12 ,  H01L23/495 ,  H01L25/00 ,  H01L23/34 ,  H01L29/74 ,  H01L29/861 ,  H01L31/111

CPC分类号： H01L24/06 ,  H01L23/49575 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  Y10S257/925

摘要： A semiconductor component includes an insulating housing. A plurality of sheet-metal mounting plates are disposed in one and the same plane and are electrically separated from one another in the housing. Semiconductor switches of a rectifier bridge are electrically conductively secured to the mounting plates. Sheet-metal connection leads are electrically connected to the semiconductor switches. At least one sheet-metal connection lead is electrically connected to the mounting plates.

摘要翻译： 半导体部件包括绝缘壳体。 多个金属板安装板被设置在同一平面中并且在壳体中彼此电分离。 整流桥的半导体开关导电地固定在安装板上。 钣金连接引线电连接到半导体开关。 至少一个金属片连接引线与安装板电连接。

公开(公告)号：US5580810A

公开(公告)日：1996-12-03

申请号：US416099

申请日：1995-04-04

申请人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

发明人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/8247

CPC分类号： H01L23/522 ,  G11C5/025 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/922 ,  Y10S257/925 ,  Y10S438/926

摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.

摘要翻译： 一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。 布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。 布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。