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    Semiconductor memory device with trench surrounding each memory cell
    1.
    发明授权
    Semiconductor memory device with trench surrounding each memory cell 失效
    具有围绕每个存储单元的沟槽的半导体存储器件

    公开(公告)号：US4672410A

    公开(公告)日：1987-06-09

    申请号：US753283

    申请日：1985-07-09

    申请人： Kenji Miura ,  Shigeru Nakajima ,  Kazushige Minegishi ,  Takashi Morie ,  Toshifumi Somatani

    发明人： Kenji Miura ,  Shigeru Nakajima ,  Kazushige Minegishi ,  Takashi Morie ,  Toshifumi Somatani

    IPC分类号： H01L21/20 ,  H01L21/225 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/94 ,  H01L27/02 ,  H01L29/04 ,  H01L29/06

    CPC分类号： H01L27/10864 ,  H01L21/2257 ,  H01L27/10841 ,  H01L29/7827 ,  H01L29/945

    摘要： A semiconductor device has memory cells respectively located at intersections of bit and word lines arranged in a matrix form, each of the memory cells being constituted by a single insulated gate transistor and a single capacitor. One memory cell is formed in an element formation region defined by each of trenches arranged in a matrix form. The capacitor has an insulating film formed along part of a side wall surface of a trench formed in at least a direction of thickness of a semiconductor substrate and a conductive layer formed along the insulating film. The transistor has a gate insulating film adjacent to the capacitor and formed along a remaining portion of the side wall surface of the trench, a gate electrode formed along the gate insulating film, and a diffusion region formed in a major surface of the semiconductor substrate which is adjacent to the gate insulating film. The semicondcutor memory device further has an isolation region between two adjacent ones of the memory cells along two adjacent ones of the bit or word lines. A method of manufacturing the semiconductor is also proposed.

    摘要翻译： 半导体器件具有分别位于以矩阵形式布置的位和字线的交点处的存储器单元，每个存储器单元由单个绝缘栅晶体管和单个电容器构成。 一个存储单元形成在由以矩阵形式布置的每个沟槽限定的元件形成区域中。 电容器具有沿至少沿着半导体衬底的厚度方向形成的沟槽的侧壁表面的一部分和沿绝缘膜形成的导电层形成的绝缘膜。 晶体管具有与电容器相邻的栅极绝缘膜，沿着沟槽的侧壁表面的剩余部分形成，沿着栅极绝缘膜形成的栅电极和形成在半导体衬底的主表面中的扩散区域 与栅极绝缘膜相邻。 半切割器存储器件还沿着位或字线中的两个相邻的存储器单元中的两个相邻存储单元之间具有隔离区。 还提出了制造半导体的方法。

    Method of manufacturing a vertical MOSFET with single surface electrodes
    2.
    发明授权
    Method of manufacturing a vertical MOSFET with single surface electrodes 失效
    制造具有单面电极的垂直MOSFET的方法

    公开(公告)号：US4683643A

    公开(公告)日：1987-08-04

    申请号：US756135

    申请日：1985-07-16

    申请人： Shigeru Nakajima ,  Kazushige Minegishi ,  Kenji Miura ,  Takashi Morie ,  Toshifumi Somatani

    发明人： Shigeru Nakajima ,  Kazushige Minegishi ,  Kenji Miura ,  Takashi Morie ,  Toshifumi Somatani

    IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L21/385 ,  H01L21/388 ,  H01L21/40

    CPC分类号： H01L29/7827 ,  Y10S148/168

    摘要： A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.

    摘要翻译： 垂直金属氧化物半导体场效应晶体管具有在半导体衬底的主表面上基本上垂直形成的沟槽，形成在包括栅极绝缘膜上的沟槽的侧壁表面的预定区域中的第一导电层，下部和上部扩散 形成在沟槽的底部的层和半导体衬底的表面层，优选地形成在上部和下部扩散层之间的半导体衬底中的沟道掺杂区域，以及形成在第二导电层中的下部扩散层 并且与第一导电层绝缘以便填充沟槽。 第一导电层用作栅电极，扩散层分别用作源/漏区。 还提出了制造垂直MOSFET的方法。

    Read-only memory and method of manufacturing the same
    3.
    发明授权
    Read-only memory and method of manufacturing the same 失效
    只读存储器及其制造方法

    公开(公告)号：US4630237A

    公开(公告)日：1986-12-16

    申请号：US759009

    申请日：1985-07-24

    申请人： Kenji Miura ,  Shigeru Nakajima ,  Kazushige Minegishi ,  Toshifumi Somatani ,  Takashi Morie ,  Tatsuo Baba

    发明人： Kenji Miura ,  Shigeru Nakajima ,  Kazushige Minegishi ,  Toshifumi Somatani ,  Takashi Morie ,  Tatsuo Baba

    IPC分类号： G11C17/08 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/112 ,  H01L27/115 ,  H01L29/78 ,  G11C11/40 ,  G11C13/00

    CPC分类号： H01L29/7827 ,  H01L2924/0002 ,  Y10S257/903

    摘要： A read-only memory has memory cells each with a vertical metal oxide semiconductor field effect transistor and a bit line. The vertical metal oxide semiconductor field effect transistor has a gate electrode serving as a word line, a source, a drain, and a vertical channel region between the source and drain constituted by first and second diffusion layers. The gate electrode is formed on a side wall of a trench, which has a pair of side walls substantially perpendicular to a major surface of a semiconductor substrate of a first conductivity type and an interconnecting bottom surface substantially perpendicular to the side wall surfaces. The first and second diffusion layers of a second conductivity type are formed in an upper portion of the semiconductor substrate and in a bottom of the trench, respectively. The bit lines are formed in a predetermined pattern. One of the first and second diffusion layers is connected to the bit line through a contact hole and the other of the first and second diffusion layers is used as a common current line. A method of manufacturing the read-only memory is also proposed.

    摘要翻译： 只读存储器具有各自具有垂直金属氧化物半导体场效应晶体管和位线的存储单元。 垂直金属氧化物半导体场效应晶体管具有用作由第一和第二扩散层构成的源极和漏极之间的字线，源极，漏极和垂直沟道区的栅电极。 栅电极形成在沟槽的侧壁上，沟槽的侧壁具有基本上垂直于第一导电类型的半导体衬底的主表面的一对侧壁和基本上垂直于侧壁表面的互连底表面。 第二导电类型的第一和第二扩散层分别形成在半导体衬底的上部和沟槽的底部。 位线以预定图案形成。 第一和第二扩散层中的一个通过接触孔连接到位线，并且第一和第二扩散层中的另一个用作公共电流线。 还提出了制造只读存储器的方法。

    Vertical MOSFET and method of manufacturing the same
    4.
    发明授权
    Vertical MOSFET and method of manufacturing the same 失效
    垂直MOSFET及其制造方法

    公开(公告)号：US4786953A

    公开(公告)日：1988-11-22

    申请号：US48702

    申请日：1987-05-12

    申请人： Takashi Morie ,  Toshifumi Somatani ,  Shigeru Nakajima ,  Kazushige Minegishi ,  Kenji Miura

    发明人： Takashi Morie ,  Toshifumi Somatani ,  Shigeru Nakajima ,  Kazushige Minegishi ,  Kenji Miura

    IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L29/04 ,  H01L29/06

    CPC分类号： H01L29/7827

    摘要： A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.

    摘要翻译： 垂直金属氧化物半导体场效应晶体管具有在半导体衬底的主表面上基本上垂直形成的沟槽，形成在包括栅极绝缘膜上的沟槽的侧壁表面的预定区域中的第一导电层，下部和上部扩散 形成在沟槽的底部的层和半导体衬底的表面层，优选地形成在上部和下部扩散层之间的半导体衬底中的沟道掺杂区域，以及形成在第二导电层中的下部扩散层 并且与第一导电层绝缘以便填充沟槽。 第一导电层用作栅电极，扩散层分别用作源/漏区。 还提出了制造垂直MOSFET的方法。

    Image generation device
    5.
    发明授权
    Image generation device 有权

    公开(公告)号：US09672432B2

    公开(公告)日：2017-06-06

    申请号：US14114665

    申请日：2012-05-23

    申请人： Kinji Yamamoto ,  Kazuya Watanabe ,  Shoko Takeda ,  Kenji Miura ,  Jun Kadowaki

    发明人： Kinji Yamamoto ,  Kazuya Watanabe ,  Shoko Takeda ,  Kenji Miura ,  Jun Kadowaki

    IPC分类号： G06K9/00 ,  G08G1/16 ,  G06T3/00 ,  G06T11/00 ,  G06T15/20 ,  H04N7/18

    CPC分类号： G06K9/00805 ,  B60R2300/607 ,  G06K9/00255 ,  G06T3/00 ,  G06T11/001 ,  G06T15/205 ,  G08G1/166 ,  H04N7/18

    摘要： An image generation device that enhances visual recognizability between a recognized 3D (three-dimensional) object and a substitute image synthesized in an area of a 3D object image which is a photographed image of the 3D object includes an image synthesis section that recognizes a 3D object present in the peripheral area of a vehicle and outputs 3D object attribute information indicative of attributes of this 3D object, determines a 3D object image area as an image area of the 3D object in the photographed image based on position information included in the 3D object attribute information, outputs at least one of a substitute image of the 3D object applied with a color based on the color information and a substitute image of the 3D object under a specified directional posture of the 3D object specified based on type information and directional posture information and generates a bird's-eye view image with a substitution image in which the substitution image outputted from a substitution image output section is synthesized at the position of the 3D object image area.

    IMAGE GENERATION DEVICE
    7.
    发明申请
    IMAGE GENERATION DEVICE 有权
    图像生成装置

    公开(公告)号：US20140063197A1

    公开(公告)日：2014-03-06

    申请号：US14114665

    申请日：2012-05-23

    申请人： Kinji Yamamoto ,  Kazuya Watanabe ,  Shoko Takeda ,  Kenji Miura ,  Jun Kadowaki

    发明人： Kinji Yamamoto ,  Kazuya Watanabe ,  Shoko Takeda ,  Kenji Miura ,  Jun Kadowaki

    IPC分类号： G06K9/00

    CPC分类号： G06K9/00805 ,  B60R2300/607 ,  G06K9/00255 ,  G06T3/00 ,  G06T11/001 ,  G06T15/205 ,  G08G1/166 ,  H04N7/18

    摘要： An image generation device that enhances visual recognizability between a recognized 3D (three-dimensional) object and a substitute image synthesized in an area of a 3D object image which is a photographed image of the 3D object includes an image synthesis section that recognizes a 3D object present in the peripheral area of a vehicle and outputs 3D object attribute information indicative of attributes of this 3D object, determines a 3D object image area as an image area of the 3D object in the photographed image based on position information included in the 3D object attribute information, outputs at least one of a substitute image of the 3D object applied with a color based on the color information and a substitute image of the 3D object under a specified directional posture of the 3D object specified based on type information and directional posture information and generates a bird's-eye view image with a substitution image in which the substitution image outputted from a substitution image output section is synthesized at the position of the 3D object image area.

    摘要翻译： 增强识别的3D（三维）物体与在3D物体的拍摄图像的3D对象图像的区域中合成的替代图像之间的视觉识别性的图像生成装置包括识别3D对象的图像合成部 存在于车辆的周边区域并输出指示该3D对象的属性的3D对象属性信息，基于3D对象属性中包含的位置信息，将3D对象图像区域确定为拍摄图像中的3D对象的图像区域 信息，基于颜色信息输出应用了颜色的3D对象的替代图像和基于类型信息和方位姿势信息指定的3D对象的指定方向姿势下的3D对象的替代图像中的至少一个，以及 用替代图像生成鸟瞰图，其中替代图像从替代图像输出 在3D对象图像区域的位置处合成图像输出部。

    LIGHT IRRADIATION DEVICE
    10.
    发明申请
    LIGHT IRRADIATION DEVICE 有权
    光照射装置

    公开(公告)号：US20110122623A1

    公开(公告)日：2011-05-26

    申请号：US13054921

    申请日：2009-06-01

    申请人： Kenji Miura

    发明人： Kenji Miura

    IPC分类号： F21S4/00

    CPC分类号： G01N21/8806 ,  G01N2201/0627

    摘要： The present invention uniforms a size of an LED substrate 2 to realize reduction of the number of parts and reduction of a manufacturing cost, and is a light irradiation device comprising: a long LED substrate 2 on which a plurality of same LEDs 21 are mounted; a chassis 3 having a substrate housing space for housing the LED substrate 2, wherein the number of LEDs 21 in which a difference between a power source voltage VE and a sum of a forward voltage Vf in the series connection of the LEDs 21 is within an allowable range is employed as the number of LED units, and the number of LEDs 21 mounted on the LED substrate 2 is a common multiple of the number of LED units determined in each of LEDs 21 of different wavelengths.

    摘要翻译： 本发明使LED基板2的尺寸均匀化，实现部件数量的减少和制造成本的降低，是一种光照射装置，包括：长LED基板2，多个相同的LED21安装在该LED基板2上; 具有用于容纳LED基板2的基板容纳空间的底架3，其中，LED 21的串联连接中的电源电压VE与正向电压Vf的和之间的差异的LED 21的数量在 采用允许范围作为LED单元的数量，并且安装在LED基板2上的LED 21的数量是在每个不同波长的LED 21中确定的LED单元的数量的公倍数。