公开(公告)号：US07015518B2

公开(公告)日：2006-03-21

申请号：US11084163

申请日：2005-03-21

申请人： Junichiro Kobayashi

发明人： Junichiro Kobayashi

IPC分类号： H01L21/0328 ,  H01L21/388

CPC分类号： H01L29/66462 ,  H01L29/42316 ,  H01L29/7783

摘要： To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.

公开(公告)号：US6030853A

公开(公告)日：2000-02-29

申请号：US106252

申请日：1993-08-13

申请人： John Harold Tregilgas ,  Arthur Monroe Turner

发明人： John Harold Tregilgas ,  Arthur Monroe Turner

IPC分类号： H01L21/388 ,  H01L31/0296 ,  H01L31/103 ,  H01L31/18 ,  H01L21/00

CPC分类号： H01L21/388 ,  H01L31/02966 ,  H01L31/1032 ,  H01L31/1832 ,  H01L31/1864 ,  Y02E10/50

摘要： A hybrid focal plane array has Hg.sub.1-x Cd.sub.x Te junction photodiodes formed in a substrate of HgCdTe which is capped by a layer of Te-rich CdTe. Type conversion of a low metal vacancy HgCdTe substrate to p-type is performed by annealing the capped substrate at a temperature sufficient to support interdiffusion between the Te-rich CdTe capping layer and the HgCdTe substrate. Use of the CdTe capping layer with a slight excess Te maintains the surface of the HgCdTe substrate in a Te-rich phase condition.

摘要翻译： 混合焦平面阵列具有形成在HgCdTe衬底中的Hg1-xCdxTe结光电二极管，其被富含Te的CdTe层覆盖。 通过在足以支持富Te的CdTe覆盖层和HgCdTe衬底之间的相互扩散的温度下退火封装的衬底来进行低金属空位HgCdTe衬底到p型的类型转换。 使用具有轻微过量的Te的CdTe覆盖层将HgCdTe衬底的表面保持在富Te相的状态。

公开(公告)号：US4244753A

公开(公告)日：1981-01-13

申请号：US106562

申请日：1979-12-26

申请人： Phyllis M. Harnack

发明人： Phyllis M. Harnack

IPC分类号： C30B31/04 ,  H01L21/388

CPC分类号： C30B31/04 ,  C30B29/48

摘要： A method for purification of Group II-VI crystals by contacting with a zinc melt.

摘要翻译： 通过与锌熔体接触来纯化II-VI族晶体的方法。

公开(公告)号：US4219369A

公开(公告)日：1980-08-26

申请号：US931007

申请日：1978-08-04

申请人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

发明人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/388 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/26

CPC分类号： H01L21/388 ,  H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/76216 ,  H01L21/76232 ,  H01L21/8222 ,  Y10S148/117 ,  Y10S148/143

摘要： The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.

摘要翻译： 本发明涉及一种制造半导体集成电路器件的方法，其目的在于减小将相邻半导体元件彼此隔离的隔离区的尺寸。 本发明的方法具有以下步骤：在衬底上形成不同导电类型的扩散杂质的沉积层与衬底的沉积层，在沉积层上形成具有孔的掩模膜，通过使用掩模膜进行蚀刻 作为扩散掩模，以蚀刻沉积层和基板下面的部分，从而形成将沉积层分成岛状沉积层部分的凹槽，并且将每个岛状沉积层中的杂质拉伸和扩散 沉积层部分以形成构成半导体元件的一部分的扩散层。

公开(公告)号：US3745073A

公开(公告)日：1973-07-10

申请号：US3745073D

申请日：1971-02-26

申请人： ZENITH RADIO CORP

发明人： KUN Z ,  ROBINSON R

IPC分类号： H01L21/383 ,  H01L21/388 ,  H01L7/62

CPC分类号： H01L21/383 ,  H01L21/388 ,  Y10S148/151 ,  Y10S252/951

摘要： P-N JUNCTIONS ARE FORMED BY SIMULTANEOUS DOPING OF A THIN SURFACE LAYER OF AN N-TYPE ZINC SELENIDE SUBSTRATE WITH ZINC AND WITH GALLIUM, INDIUM OR THALLIUM. DOPING MAY BE EFFECTED BY VAPOR PHASE IN-DIFFUSION OR BY SUBMERSION OF THE SUBSTRATE IN AN ALLOY MELT CONTAINING BOTH DOPANTS.

公开(公告)号：US09818856B2

公开(公告)日：2017-11-14

申请号：US14347863

申请日：2012-10-17

申请人： DENSO CORPORATION

发明人： Shinichi Hoshi ,  Shoji Mizuno ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Kazuyoshi Tomita ,  Kenji Ito

IPC分类号： H01L27/06 ,  H01L29/20 ,  H01L21/8234 ,  H01L29/16 ,  H01L21/388 ,  H01L29/15 ,  H01H3/20 ,  H01L27/07 ,  H01L29/74 ,  H01L29/778 ,  H01L29/66 ,  H01L21/762 ,  H01L29/861 ,  H01L29/06

CPC分类号： H01L29/7787 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861

摘要： A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.

公开(公告)号：US4902582A

公开(公告)日：1990-02-20

申请号：US300186

申请日：1989-01-23

申请人： Minoru Inoue

发明人： Minoru Inoue

IPC分类号： H01L21/388 ,  H01L21/28 ,  H01L21/285 ,  H01L29/45

CPC分类号： H01L29/456 ,  H01L21/28512 ,  Y10T428/12674 ,  Y10T428/12736

摘要： A semiconductor device comprising a metallized layer formed on a silicon substrate, wherein said metallized layer is an aluminum alloy consisting essentially of aluminum, silicon and at least one element selected from the group consisting of titanium, vanadium, chromium, tungsten, and phosphorus the amount of silicon being 1.0% to 3.0% by weight, the amount of said selected element corresponding to the relative service life required of the metallized layer, said required service life being 10 times that of a metallized layer having the same composition as that of the above-mentioned metallized layer except for being free from said element, and the rest being aluminum. For example, the metallized layer may contain at least 0.04% and less than 0.10% by weight of titanium, 1.0% by weight of silicon, and the rest aluminum.

摘要翻译： 一种半导体器件，包括形成在硅衬底上的金属化层，其中所述金属化层是基本上由铝，硅和至少一种选自钛，钒，铬，钨和磷的元素组成的铝合金，其量 的硅为1.0〜3.0重量％，所述选定元素的量相当于金属化层所需的相对使用寿命，所述使用寿命为与上述相同组成的金属化层的10倍 所述金属化层除了不含所述元素，其余为铝。 例如，金属化层可以含有至少0.04重量％且小于0.10重量％的钛，1.0重量％的硅和其余的铝。

公开(公告)号：US4582722A

公开(公告)日：1986-04-15

申请号：US666954

申请日：1984-10-30

申请人： Lester W. Herron ,  Ananda H. Kumar ,  Robert W. Nufer

发明人： Lester W. Herron ,  Ananda H. Kumar ,  Robert W. Nufer

IPC分类号： H01L23/12 ,  C23C10/04 ,  H01L21/388 ,  H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K3/24 ,  B05D3/12 ,  B05D5/12 ,  C23C14/00

CPC分类号： H01L21/4846 ,  C23C10/04 ,  H05K3/246 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/0743 ,  H05K3/048

摘要： Disclosed is a maskless metal cladding process for plating an existing metallurgical pattern by utilizing a protective layer to isolate those areas of underlying metallurgy on which additional metal plating is not desired. The layer acts as an isolation barrier to protect the underlying metallurgy from deposition and subsequent diffusion of the heavy metal (e.g., gold) overlay. The composition of the protective layer is selected as one having sufficient mechanical integrity to withstand process handling and support the gold overlay and having the thermal integrity to withstand the high temperatures reached during metal sputtering and diffusion processes. The isolation barrier layer has an organic component as a binder which thermally decomposes, either in a heating step before metal deposition or during the diffusion cycle, leaving no carbonaceous residue but leaving an inert, inorganic standoff to support the metal. After diffusion of the metal, the remaining inorganic standoff layer, overlying metal and any undiffused metal remaining on the non-patterned substrate is easily removed by a standard technique, such as ultrasonics.

摘要翻译： 公开了一种无掩模金属包覆工艺，用于通过利用保护层来电镀现有的冶金图案，以隔离不期望附加金属镀覆的下方冶金的那些区域。 该层用作隔离屏障，以保护底层冶金不沉积和随后扩散重金属（例如，金）覆盖层。 保护层的组成选择为具有足够的机械完整性的组合物，以承受工艺处理并支撑金覆层并具有耐热金属溅射和扩散过程中达到的高温的热完整性。 隔离阻挡层具有作为粘合剂的有机组分，其在金属沉积之前的加热步骤或扩散循环期间热分解，不留下含碳残留物，而留下惰性的无机支架以支撑金属。 在金属扩散之后，剩余的无机隔离层，覆盖的金属和残留在非图案化衬底上的任何未扩散的金属都可以通过诸如超声波的标准技术容易地去除。

公开(公告)号：US4520554A

公开(公告)日：1985-06-04

申请号：US676948

申请日：1984-11-30

申请人： Albert W. Fisher

发明人： Albert W. Fisher

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/388

CPC分类号： H01L21/76877 ,  H01L23/53214 ,  H01L2924/0002

摘要： A semiconductor device having a multi-level metallization system wherein the first level is of aluminum containing up to 3 of percent silicon and the second level is either aluminum or aluminum containing silicon in an amount less than that contained in the first level. The two levels where they contact each other are sintered together with some of the silicon from the first level being diffused into the second level so that the second level has a region adjacent the junction between the two levels which has a higher content of silicon than the remaining portion of the second level. When making the device, the surface of the first level where it is to be joined with the second level is etched to remove some of the aluminum, but not the silicon, which roughens this surface. The second level is applied on this roughened surface and the device is heated to sinter the two levels together and diffuse the silicon into the second level.

摘要翻译： 一种具有多级金属化系统的半导体器件，其中第一级为含有至多3％的硅的铝，而第二级为含有少于第一级含量的铝或铝的硅。 它们彼此接触的两个层级被烧结在一起，其中来自第一层的一些硅被扩散到第二层中，使得第二层具有邻近两层之间的结的区域，这两层之间的接合点具有比 二级剩余部分。 当制造该装置时，蚀刻要与第二层连接的第一层的表面以除去一些铝，而不是粗糙化该表面的硅。 将第二级施加在该粗糙表面上，并且加热该装置以将两个层结合在一起并将硅扩散到第二层。

公开(公告)号：US3670220A

公开(公告)日：1972-06-13

申请号：US3670220D

申请日：1971-02-26

申请人： ZENITH RADIO CORP

发明人： KUN ZOLTAN K ,  ROBINSON ROBERT J

IPC分类号： H01L21/38 ,  H01L21/383 ,  H01L21/388 ,  H01L33/00 ,  H01L33/28 ,  H01L7/62

CPC分类号： H01L33/285 ,  H01L21/38 ,  H01L21/383 ,  H01L21/388 ,  H01L33/0066 ,  Y10S252/95 ,  Y10S252/951

摘要： PN-junctions are formed in a wide band gap zinc chalcogenide (i.e., zinc selenide, zinc sulfide or a zinc sulfo-selenide by pre-doping a surface layer of an N-doped zinc chalcogenide substrate by in-diffusion of a Group III metal to condition it for conversion to P-type conductivity, and converting the predoped surface layer to P-type conductivity by doping it with zinc. The pre-doping and conversion steps may be conducted either simultaneously or sequentially. Well defined PN-junctions are produced, with majority carrier concentrations on the Pconductivity side of the junction of at least 1016 to 1017 holes per cubic centimeter.

摘要翻译： 在宽带隙锌硫族化物（即，硒化锌，硫化锌或硫化锌锌）中通过在III族金属的扩散中预掺杂N-掺杂的硫属硫属化物衬底的表面层形成PN结 将其转化为P型导电性，并通过用锌掺杂将预掺杂表面层转化为P型导电性，预掺杂和转化步骤可以同时或顺序进行，定义良好的PN结 在交联的P导电侧具有多数载流子浓度至少为1016至1017个孔/立方厘米的载流子浓度。