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1.发明授权
公开(公告)号：US4683643A
公开(公告)日：1987-08-04
申请号：US756135
申请日：1985-07-16
IPC分类号： H01L29/417 , H01L29/78 , H01L21/385 , H01L21/388 , H01L21/40
CPC分类号： H01L29/7827 , Y10S148/168
摘要： A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.
摘要翻译： 垂直金属氧化物半导体场效应晶体管具有在半导体衬底的主表面上基本上垂直形成的沟槽，形成在包括栅极绝缘膜上的沟槽的侧壁表面的预定区域中的第一导电层，下部和上部扩散 形成在沟槽的底部的层和半导体衬底的表面层，优选地形成在上部和下部扩散层之间的半导体衬底中的沟道掺杂区域，以及形成在第二导电层中的下部扩散层 并且与第一导电层绝缘以便填充沟槽。 第一导电层用作栅电极，扩散层分别用作源/漏区。 还提出了制造垂直MOSFET的方法。
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2.发明授权
公开(公告)号：US4672410A
公开(公告)日：1987-06-09
申请号：US753283
申请日：1985-07-09
IPC分类号： H01L21/20 , H01L21/225 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/94 , H01L27/02 , H01L29/04 , H01L29/06
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841 , H01L29/7827 , H01L29/945
摘要： A semiconductor device has memory cells respectively located at intersections of bit and word lines arranged in a matrix form, each of the memory cells being constituted by a single insulated gate transistor and a single capacitor. One memory cell is formed in an element formation region defined by each of trenches arranged in a matrix form. The capacitor has an insulating film formed along part of a side wall surface of a trench formed in at least a direction of thickness of a semiconductor substrate and a conductive layer formed along the insulating film. The transistor has a gate insulating film adjacent to the capacitor and formed along a remaining portion of the side wall surface of the trench, a gate electrode formed along the gate insulating film, and a diffusion region formed in a major surface of the semiconductor substrate which is adjacent to the gate insulating film. The semicondcutor memory device further has an isolation region between two adjacent ones of the memory cells along two adjacent ones of the bit or word lines. A method of manufacturing the semiconductor is also proposed.
摘要翻译： 半导体器件具有分别位于以矩阵形式布置的位和字线的交点处的存储器单元，每个存储器单元由单个绝缘栅晶体管和单个电容器构成。 一个存储单元形成在由以矩阵形式布置的每个沟槽限定的元件形成区域中。 电容器具有沿至少沿着半导体衬底的厚度方向形成的沟槽的侧壁表面的一部分和沿绝缘膜形成的导电层形成的绝缘膜。 晶体管具有与电容器相邻的栅极绝缘膜，沿着沟槽的侧壁表面的剩余部分形成，沿着栅极绝缘膜形成的栅电极和形成在半导体衬底的主表面中的扩散区域 与栅极绝缘膜相邻。 半切割器存储器件还沿着位或字线中的两个相邻的存储器单元中的两个相邻存储单元之间具有隔离区。 还提出了制造半导体的方法。
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公开(公告)号：US4630237A
公开(公告)日：1986-12-16
申请号：US759009
申请日：1985-07-24
申请人： Kenji Miura , Shigeru Nakajima , Kazushige Minegishi , Toshifumi Somatani , Takashi Morie , Tatsuo Baba
发明人： Kenji Miura , Shigeru Nakajima , Kazushige Minegishi , Toshifumi Somatani , Takashi Morie , Tatsuo Baba
IPC分类号： G11C17/08 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/78 , G11C11/40 , G11C13/00
CPC分类号： H01L29/7827 , H01L2924/0002 , Y10S257/903
摘要： A read-only memory has memory cells each with a vertical metal oxide semiconductor field effect transistor and a bit line. The vertical metal oxide semiconductor field effect transistor has a gate electrode serving as a word line, a source, a drain, and a vertical channel region between the source and drain constituted by first and second diffusion layers. The gate electrode is formed on a side wall of a trench, which has a pair of side walls substantially perpendicular to a major surface of a semiconductor substrate of a first conductivity type and an interconnecting bottom surface substantially perpendicular to the side wall surfaces. The first and second diffusion layers of a second conductivity type are formed in an upper portion of the semiconductor substrate and in a bottom of the trench, respectively. The bit lines are formed in a predetermined pattern. One of the first and second diffusion layers is connected to the bit line through a contact hole and the other of the first and second diffusion layers is used as a common current line. A method of manufacturing the read-only memory is also proposed.
摘要翻译： 只读存储器具有各自具有垂直金属氧化物半导体场效应晶体管和位线的存储单元。 垂直金属氧化物半导体场效应晶体管具有用作由第一和第二扩散层构成的源极和漏极之间的字线，源极，漏极和垂直沟道区的栅电极。 栅电极形成在沟槽的侧壁上，沟槽的侧壁具有基本上垂直于第一导电类型的半导体衬底的主表面的一对侧壁和基本上垂直于侧壁表面的互连底表面。 第二导电类型的第一和第二扩散层分别形成在半导体衬底的上部和沟槽的底部。 位线以预定图案形成。 第一和第二扩散层中的一个通过接触孔连接到位线，并且第一和第二扩散层中的另一个用作公共电流线。 还提出了制造只读存储器的方法。
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公开(公告)号：US4786953A
公开(公告)日：1988-11-22
申请号：US48702
申请日：1987-05-12
CPC分类号： H01L29/7827
摘要： A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.
摘要翻译： 垂直金属氧化物半导体场效应晶体管具有在半导体衬底的主表面上基本上垂直形成的沟槽，形成在包括栅极绝缘膜上的沟槽的侧壁表面的预定区域中的第一导电层，下部和上部扩散 形成在沟槽的底部的层和半导体衬底的表面层，优选地形成在上部和下部扩散层之间的半导体衬底中的沟道掺杂区域，以及形成在第二导电层中的下部扩散层 并且与第一导电层绝缘以便填充沟槽。 第一导电层用作栅电极，扩散层分别用作源/漏区。 还提出了制造垂直MOSFET的方法。
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公开(公告)号：US4786954A
公开(公告)日：1988-11-22
申请号：US110616
申请日：1987-10-19
IPC分类号： H01L21/74 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10832 , H01L21/743
摘要： A semiconductor memory device has a semiconductor substrate of one conductivity type in which a plurality of memory cells are formed, each of the plurality of memory cells including at least one capacitor and having a trench which is formed from one major surface of the semiconductor substrate so as to surround at least one memory cell, wherein a first insulating film having element isolation properties is formed on a bottom and most areas of side wall surfaces of the trench, a first conductive film serving as one electrode of the capacitor is formed on the side wall of the first insulating film and an exposed portion of the semiconductor substrate which is not covered with the first insulating film, a second insulating film is formed on the first conductive film, and a second conductive film serving as the other electrode of the capacitor is formed on the second insulating film.
摘要翻译： 半导体存储器件具有其中形成有多个存储单元的一种导电类型的半导体衬底，所述多个存储单元中的每一个包括至少一个电容器，并且具有由半导体衬底的一个主表面形成的沟槽， 为了围绕至少一个存储单元，其中在沟槽的侧壁表面的底部和大部分区域上形成具有元件隔离性能的第一绝缘膜，在电容器的一侧形成用作电容器的一个电极的第一导电膜 第一绝缘膜的壁和未被第一绝缘膜覆盖的半导体衬底的暴露部分，在第一导电膜上形成第二绝缘膜，并且用作电容器的另一个电极的第二导电膜为 形成在第二绝缘膜上。
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公开(公告)号：US4645564A
公开(公告)日：1987-02-24
申请号：US712860
申请日：1985-03-18
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/94 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L29/945 , H01L27/10829 , Y10S148/05
摘要： A semiconductor device with a metal-insulator-semiconductor capacitor has:a semiconductor substrate having a predetermined conductivity type and serving as one electrode of the metal-insulator-semiconductor capacitor, the semiconductor substrate being provided with a trench of a cross-sectionally rectangular shape which extends along a direction of thickness of the semiconductor substrate from a major surface thereof;a doped semiconductor layer formed along at least side wall surfaces of the trench, the semiconductor layer, which is formed by deposition and etching, being provided with an outer surface, starting to extend in a rounded shape from major surface portions of the semiconductor substrate and extending substantially parallel to the side wall surfaces of the trench, and a recess, which is defined by the semiconductor layer, having round corners at the bottom;a dielectric insulating layer formed on an exposed surface including the major surface of the semiconductor substrate and the outer surface of the semiconductor layer; anda conductive layer formed on the insulating layer to bury trench and serving as the other electrode.
摘要翻译： 具有金属 - 绝缘体 - 半导体电容器的半导体器件具有：具有预定导电类型并用作金属 - 绝缘体 - 半导体电容器的一个电极的半导体衬底，所述半导体衬底设置有横截面矩形形状的沟槽 其从半导体衬底的主表面沿着半导体衬底的厚度方向延伸; 沿着沟槽的至少侧壁表面形成的掺杂半导体层，通过沉积和蚀刻形成的半导体层设置有从半导体衬底的主表面开始以圆形形状延伸的外表面，以及 基本上平行于沟槽的侧壁表面延伸，以及由半导体层限定的在底部具有圆角的凹槽; 形成在包括半导体衬底的主表面和半导体层的外表面的暴露表面上的介电绝缘层; 以及形成在绝缘层上以埋设沟槽并用作另一电极的导电层。
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公开(公告)号：US07911369B2
公开(公告)日：2011-03-22
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译： 流水线式AD转换器（1）包括多个转换级（11,11 ...）。 在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。 数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。 充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2） 以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。 放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。
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公开(公告)号：US20100149010A1
公开(公告)日：2010-06-17
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译： 流水线式AD转换器（1）包括多个转换级（11,11 ...）。 在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。 数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。 充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2） 以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。 放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。
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9.发明申请公开(公告)号：US20090115502A1
公开(公告)日：2009-05-07
申请号：US12093393
申请日：2007-09-04
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.
摘要翻译： 电流镜电路10形成为具有1：m的电流比（晶体管尺寸比）。 同样，各对nMOS晶体管MN1，MN3和nMOS晶体管MN2，MN4形成为具有1：m的电流比。 从电流镜电路10输出的两个电流分别分配给两个。 在nMOS晶体管MN2，MN4中流动的分布电流相加，然后被允许流入一个电阻器R2。 因此，对于电阻器R2，例如当m = 1时，只有一个双电流的电流就足够了。 这轻而易举地减少了四分之一的必要阻力。
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公开(公告)号：US20080315933A1
公开(公告)日：2008-12-25
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K3/00
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。
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