公开(公告)号：US06757784B2

公开(公告)日：2004-06-29

申请号：US09966586

申请日：2001-09-28

申请人： Shih-Lien L. Lu ,  Dinesh Somasekhar ,  Konrad Lai

发明人： Shih-Lien L. Lu ,  Dinesh Somasekhar ,  Konrad Lai

IPC分类号： G06F1200

CPC分类号： G06F12/0893

摘要： The present invention is in the field of memory architecture and management. More particularly, the present invention provides a method, apparatus, system, and machine-readable medium to hide refresh cycles of a memory array such as dynamic random access memory.

摘要翻译： 本发明在存储器架构和管理领域。 更具体地，本发明提供了一种隐藏诸如动态随机存取存储器之类的存储器阵列的刷新周期的方法，装置，系统和机器可读介质。

公开(公告)号：US06671780B1

公开(公告)日：2003-12-30

申请号：US09586548

申请日：2000-05-31

申请人： Shih-Lien L. Lu ,  Konrad Lai

发明人： Shih-Lien L. Lu ,  Konrad Lai

IPC分类号： G06F1208

CPC分类号： G06F12/123

摘要： A modified least recently allocated cache enables a computer to use a modified least recently allocated cache block replacement policy. In a first embodiment, an indicator of the least recently allocated cache block is tracked. When a cache block is referenced, the referenced cache block is compared with the least recently allocated cache block indicator. If the two identify the same cache block, the least recently allocated cache block indicator is adjusted to identify a different cache block. This adjustment prevents the most recently referenced cache block from being replaced. In an alternative embodiment, the most recently referenced cache block is similarly tracked, but the least recently allocated cache block is not immediately adjusted. Only when a new cache block is to be a located are the least recently allocated cache block indicator and the most recently referenced cache block indicator compared. Then, if the two indicators identify the same block, a different cache block is selected for the allocating the new cache block.

摘要翻译： 经修改的最近最近分配的高速缓存使得计算机能够使用经修改的最近最少分配的高速缓存块替换策略。 在第一实施例中，跟踪最近分配的高速缓存块的指示符。 当引用高速缓存块时，引用的高速缓存块与最近分配的高速缓存块指示符进行比较。 如果两者识别相同的缓存块，则调整最近最少分配的高速缓存块指示符以识别不同的高速缓存块。 此调整可防止最近引用的缓存块被替换。 在替代实施例中，类似地跟踪最近引用的高速缓存块，但是不会立即调整最近最少分配的高速缓存块。 只有当新的高速缓存块要被定位时，才最近分配的高速缓存块指示符和最近被引用的高速缓存块指示符进行比较。 然后，如果两个指示符标识相同的块，则选择不同的高速缓存块来分配新的高速缓存块。

公开(公告)号：US06608775B2

公开(公告)日：2003-08-19

申请号：US10067491

申请日：2002-02-04

申请人： Shih-Lien L. Lu ,  Konrad Lai

发明人： Shih-Lien L. Lu ,  Konrad Lai

IPC分类号： G11C1100

CPC分类号： G11C8/16

摘要： A circuit including a plurality of latches including feedback control circuitry and a plurality of data input terminals and data output terminals respectively coupled to alternative sides of said plurality of latches.

公开(公告)号：US06430083B1

公开(公告)日：2002-08-06

申请号：US09606577

申请日：2000-06-28

申请人： Shih-Lien L. Lu ,  Konrad Lai

发明人： Shih-Lien L. Lu ,  Konrad Lai

IPC分类号： G11C1100

CPC分类号： G11C8/16

摘要： A circuit including a plurality of latches including feedback control circuitry and a plurality of data input terminals and data output terminals respectively coupled to alternative sides of said plurality of latches.

摘要翻译： 包括多个锁存器的电路包括反馈控制电路和分别耦合到所述多个锁存器的替代侧的多个数据输入端子和数据输出端子。

公开(公告)号：US20050097276A1

公开(公告)日：2005-05-05

申请号：US10691342

申请日：2003-10-21

申请人： Shih-Lien Lu ,  Dinesh Somasekhar ,  Konrad Lai

发明人： Shih-Lien Lu ,  Dinesh Somasekhar ,  Konrad Lai

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0893

摘要： The present invention is in the field of memory architecture and management. More particularly, the present invention provides a method, apparatus, system, and machine-readable medium to hide refresh cycles of a memory array such as dynamic random access memory.

摘要翻译： 本发明在存储器架构和管理领域。 更具体地，本发明提供了一种隐藏诸如动态随机存取存储器之类的存储器阵列的刷新周期的方法，装置，系统和机器可读介质。

公开(公告)号：US20150006717A1

公开(公告)日：2015-01-01

申请号：US14126313

申请日：2013-06-27

申请人： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

发明人： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

IPC分类号： H04L12/26

CPC分类号： G06F9/30189 ,  G06F11/3636

摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

摘要翻译： 根据本文公开的实施例，提供了用于跟踪指令跟踪系统中的处理设备的模式的系统和方法。 该方法可以包括接收处理设备的当前执行模式中的改变的指示。 该方法还可以包括确定接收到的指示的当前执行模式不同于IT模块先前生成的第一执行模式（EM）分组的执行模式的值。 该方法还可以包括基于确定当前执行模式不同而生成第二EM分组，其提供处理设备的当前执行模式的值以指示用于跟踪中的指令的执行模式的改变 由IT模块生成。 该方法还可以包括在分组日志中生成具有n位模式模式的事务存储器（TMX）分组。 n至少为2，n位模式表示TMX操作的事务状态。

公开(公告)号：US08180977B2

公开(公告)日：2012-05-15

申请号：US11394687

申请日：2006-03-30

申请人： Ravi Rajwar ,  Haitham H. Akkary ,  Konrad Lai

发明人： Ravi Rajwar ,  Haitham H. Akkary ,  Konrad Lai

IPC分类号： G06F12/00

CPC分类号： G06F9/526 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863 ,  G06F12/0802 ,  G06F13/1626

摘要： Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide nested recovery in case of an error, fault, etc. in accordance with a described embodiment.

摘要翻译： 描述了在乱序处理器中提供事务性存储器执行的方法和装置。 在一个实施例中，存储的值对应于未提交的事务存储器访问请求的数量。 根据所描述的实施例，存储的值可以用于在错误，故障等的情况下提供嵌套恢复。

公开(公告)号：US06507895B1

公开(公告)日：2003-01-14

申请号：US09539665

申请日：2000-03-30

申请人： Hong Wang ,  Ralph Kling ,  Jeff Baxter ,  Konrad Lai

发明人： Hong Wang ,  Ralph Kling ,  Jeff Baxter ,  Konrad Lai

IPC分类号： G06F1202

CPC分类号： G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6028

摘要： An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of addresses. The second set of addresses follows the first set of addresses. The second set of addresses are calculated based on a fixed stride, where the second set of addresses are associated with data from a first stream. A plurality of addresses is generated for a third set of addresses. The third set of addresses follows the first set of addresses. Each address in the third set of addresses is generated by tracing a link associated with another address in the third set of addresses. The third set of addresses is associated with data from a second stream.

摘要翻译： 本发明的实施例提供了一种用于存储器访问分界的装置。 数据从第一高速缓存访​​问，第一高速缓存包括第一组地址中的第一组地址和相应的数据。 为第二组地址生成多个地址。 第二组地址遵循第一组地址。 基于固定步幅计算第二组地址，其中第二组地址与来自第一流的数据相关联。 为第三组地址生成多个地址。 第三组地址遵循第一组地址。 通过跟踪与第三组地址中的另一地址相关联的链接来生成第三组地址中的每个地址。 第三组地址与来自第二个流的数据相关联。

公开(公告)号：US06711662B2

公开(公告)日：2004-03-23

申请号：US09823251

申请日：2001-03-29

申请人： Jih-Kwon Peir ,  Konrad Lai

发明人： Jih-Kwon Peir ,  Konrad Lai

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F2212/507

摘要： A shared-memory system includes processing modules communicating with each other through a network. Each of the processing modules includes a processor, a cache, and a memory unit that is locally accessible by the processor and remotely accessible via the network by all other processors. A home directory records states and locations of data blocks in the memory unit. A prediction facility that contains reference history information of the data blocks predicts a next requester of a number of the data blocks that have been referenced recently. The next requester is informed by the prediction facility of the current owner of the data block. As a result, the next requester can issue a request to the current owner directly without an additional hop through the home directory.

摘要翻译： 共享存储器系统包括通过网络彼此通信的处理模块。 每个处理模块包括处理器，高速缓存和存储器单元，其可由处理器本地访问并且可被所有其他处理器经由网络远程访问。 主目录记录存储器单元中的数据块的状态和位置。 包含数据块的参考历史信息的预测设备预测最近已被引用的数个数据块的下一个请求者。 下一个请求者由数据块的当前所有者的预测设备通知。 因此，下一个请求者可以直接向当前所有者发出请求，而无需通过主目录进行额外的跳转。

公开(公告)号：US5796977A

公开(公告)日：1998-08-18

申请号：US688238

申请日：1996-07-29

申请人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

发明人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/18 ,  G06F12/0831

摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

摘要翻译： 描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。 计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。 此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。