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    TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS
    1.
    发明申请
    TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS 审中-公开
    指令跟踪系统中处理设备的跟踪模式

    公开(公告)号：US20150006717A1

    公开(公告)日：2015-01-01

    申请号：US14126313

    申请日：2013-06-27

    申请人： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

    发明人： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

    IPC分类号： H04L12/26

    CPC分类号： G06F9/30189 ,  G06F11/3636

    摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

    摘要翻译： 根据本文公开的实施例，提供了用于跟踪指令跟踪系统中的处理设备的模式的系统和方法。 该方法可以包括接收处理设备的当前执行模式中的改变的指示。 该方法还可以包括确定接收到的指示的当前执行模式不同于IT模块先前生成的第一执行模式（EM）分组的执行模式的值。 该方法还可以包括基于确定当前执行模式不同而生成第二EM分组，其提供处理设备的当前执行模式的值以指示用于跟踪中的指令的执行模式的改变 由IT模块生成。 该方法还可以包括在分组日志中生成具有n位模式模式的事务存储器（TMX）分组。 n至少为2，n位模式表示TMX操作的事务状态。

    Transactional memory virtualization
    4.
    发明授权
    Transactional memory virtualization 有权
    事务性内存虚拟化

    公开(公告)号：US08180967B2

    公开(公告)日：2012-05-15

    申请号：US11394622

    申请日：2006-03-30

    申请人： Ravi Rajwar ,  Haitham H. Akkary ,  Konrad Lai

    发明人： Ravi Rajwar ,  Haitham H. Akkary ,  Konrad Lai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0842 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/467

    摘要： Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.

    摘要翻译： 描述了以虚拟化模式提供事务性存储器执行的方法和装置。 在一个实施例中，对应于事务存储器访问请求的数据可以在与事务存储器访问请求相对应的操作引起溢出并且可以针对溢出的发生更新存储的值之后存储在存储器的一部分中。

    Using hardware checkpoints to support software based speculation
    5.
    发明申请
    Using hardware checkpoints to support software based speculation 审中-公开
    使用硬件检查点来支持基于软件的猜测

    公开(公告)号：US20080244544A1

    公开(公告)日：2008-10-02

    申请号：US11729724

    申请日：2007-03-29

    申请人： Naveen Neelakantam ,  Craig Zilles ,  Uma Srinivasan ,  Suresh Srinivas ,  Ravi Rajwar ,  Konrad Lai

    发明人： Naveen Neelakantam ,  Craig Zilles ,  Uma Srinivasan ,  Suresh Srinivas ,  Ravi Rajwar ,  Konrad Lai

    IPC分类号： G06F9/45

    CPC分类号： G06F8/443

    摘要： Hardware checkpoints may be used to mark software-based speculation regions. An instruction may be provided at the beginning of a speculation region and at the end of the speculation region. If an exception occurs during the speculation region, a hardware rollback may be occurred. The hardware rollback rolls back to the instruction at the beginning of the speculation region. The hardware may take a checkpoint by taking a register snapshot and treating future memory updates as tentative. When the instruction marking the end of the speculation is reached, all the tentative memory updates are committed and the previously taken register snapshot is discarded.

    摘要翻译： 硬件检查点可用于标记基于软件的推测区域。 可以在投机区域的开始处和投机区域的末尾提供指令。 如果在推测区域发生异常，则可能会发生硬件回滚。 硬件回滚回滚到投机区域开头的指令。 硬件可以通过注册快照并将未来的内存更新视为暂时性来检查点。 当达到臆测结束的指示时，所有暂时的内存更新被提交，并且先前注册的注册快照被丢弃。

    Transactional memory virtualization
    6.
    发明申请
    Transactional memory virtualization 有权
    事务性内存虚拟化

    公开(公告)号：US20070239942A1

    公开(公告)日：2007-10-11

    申请号：US11394622

    申请日：2006-03-30

    申请人： Ravi Rajwar ,  Haitham Akkary ,  Konrad Lai

    发明人： Ravi Rajwar ,  Haitham Akkary ,  Konrad Lai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0842 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/467

    摘要： Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.

    摘要翻译： 描述了以虚拟化模式提供事务性存储器执行的方法和装置。 在一个实施例中，对应于事务存储器访问请求的数据可以在与事务存储器访问请求相对应的操作引起溢出并且可以针对溢出的发生更新存储的值之后存储在存储器的一部分中。

    Method and apparatus for access demarcation
    7.
    发明授权
    Method and apparatus for access demarcation 失效
    访问分界的方法和装置

    公开(公告)号：US06507895B1

    公开(公告)日：2003-01-14

    申请号：US09539665

    申请日：2000-03-30

    申请人： Hong Wang ,  Ralph Kling ,  Jeff Baxter ,  Konrad Lai

    发明人： Hong Wang ,  Ralph Kling ,  Jeff Baxter ,  Konrad Lai

    IPC分类号： G06F1202

    CPC分类号： G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6028

    摘要： An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of addresses. The second set of addresses follows the first set of addresses. The second set of addresses are calculated based on a fixed stride, where the second set of addresses are associated with data from a first stream. A plurality of addresses is generated for a third set of addresses. The third set of addresses follows the first set of addresses. Each address in the third set of addresses is generated by tracing a link associated with another address in the third set of addresses. The third set of addresses is associated with data from a second stream.

    摘要翻译： 本发明的实施例提供了一种用于存储器访问分界的装置。 数据从第一高速缓存访​​问，第一高速缓存包括第一组地址中的第一组地址和相应的数据。 为第二组地址生成多个地址。 第二组地址遵循第一组地址。 基于固定步幅计算第二组地址，其中第二组地址与来自第一流的数据相关联。 为第三组地址生成多个地址。 第三组地址遵循第一组地址。 通过跟踪与第三组地址中的另一地址相关联的链接来生成第三组地址中的每个地址。 第三组地址与来自第二个流的数据相关联。

    Multiprocessor cache coherence management
    8.
    发明授权
    Multiprocessor cache coherence management 有权
    多处理器缓存一致性管理

    公开(公告)号：US06711662B2

    公开(公告)日：2004-03-23

    申请号：US09823251

    申请日：2001-03-29

    申请人： Jih-Kwon Peir ,  Konrad Lai

    发明人： Jih-Kwon Peir ,  Konrad Lai

    IPC分类号： G06F1200

    CPC分类号： G06F12/0817 ,  G06F2212/507

    摘要： A shared-memory system includes processing modules communicating with each other through a network. Each of the processing modules includes a processor, a cache, and a memory unit that is locally accessible by the processor and remotely accessible via the network by all other processors. A home directory records states and locations of data blocks in the memory unit. A prediction facility that contains reference history information of the data blocks predicts a next requester of a number of the data blocks that have been referenced recently. The next requester is informed by the prediction facility of the current owner of the data block. As a result, the next requester can issue a request to the current owner directly without an additional hop through the home directory.

    摘要翻译： 共享存储器系统包括通过网络彼此通信的处理模块。 每个处理模块包括处理器，高速缓存和存储器单元，其可由处理器本地访问并且可被所有其他处理器经由网络远程访问。 主目录记录存储器单元中的数据块的状态和位置。 包含数据块的参考历史信息的预测设备预测最近已被引用的数个数据块的下一个请求者。 下一个请求者由数据块的当前所有者的预测设备通知。 因此，下一个请求者可以直接向当前所有者发出请求，而无需通过主目录进行额外的跳转。

    Highly pipelined bus architecture
    9.
    发明授权
    Highly pipelined bus architecture 失效
    高度流水线总线架构

    公开(公告)号：US5796977A

    公开(公告)日：1998-08-18

    申请号：US688238

    申请日：1996-07-29

    申请人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

    发明人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

    IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/18 ,  G06F12/0831

    摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

    摘要翻译： 描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。 计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。 此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

    Mixed-precision floating point operations from a single instruction opcode
    10.
    发明授权
    Mixed-precision floating point operations from a single instruction opcode 失效
    来自单指令操作码的混合精度浮点运算

    公开(公告)号：US4823260A

    公开(公告)日：1989-04-18

    申请号：US119547

    申请日：1987-11-12

    申请人： Michael T. Imel ,  Konrad Lai ,  Glenford J. Myers ,  Randy Steck ,  James Valerio

    发明人： Michael T. Imel ,  Konrad Lai ,  Glenford J. Myers ,  Randy Steck ,  James Valerio

    IPC分类号： G06F7/57 ,  G06F7/48

    CPC分类号： G06F7/483 ,  G06F2207/3816 ,  G06F7/49957

    摘要： Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.

    摘要翻译： 用于从单个指令操作码在微处理器的浮点单元中执行混合精度计算的装置。 可以将80位浮点寄存器（44）指定为浮点指令的源地址或目标地址。 当目的地的地址范围指示（26）指定浮点寄存器时，该操作的结果不会舍入到指令指定的精度，而是舍入（58）到扩展的80位精度并加载到 浮点寄存器（FP-44）。 当源地址范围指示（26）FP寄存器被寻址时，无论指令指定的精度如何，数据都以扩展精度从FP寄存器加载。 以这种方式，可以使用实际和长期实际的操作来使用扩展精度数字，而无需在操作码中明确指定。