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公开(公告)号：US06996006B2
公开(公告)日：2006-02-07
申请号：US10873253
申请日：2004-06-23
IPC分类号： G11C16/04
摘要： A memory mat is provided separately from a memory mat that is a normal memory area, and data therein cannot be read from the outside. In a page buffer, information input from the outside is stored. A comparing circuit compares security information stored in memory mat with information stored in page buffer, and the comparison result is output to the outside as a status. Even when unauthorized copying is performed, information in memory mat is not copied. Therefore, an external apparatus can easily determine whether or not the semiconductor memory is an unauthorized copy by referring to the status.
摘要翻译： 与作为正常存储区域的存储器垫分开提供存储器垫，并且其中的数据不能从外部读取。 在页面缓冲器中，存储从外部输入的信息。 比较电路将存储器中存储的安全信息与存储在页缓冲器中的信息进行比较，并将比较结果输出到外部作为状态。 即使执行未经授权的复制，也不会复制内存条中的信息。 因此，外部设备可以通过参考状态来容易地确定半导体存储器是否是未经授权的拷贝。
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2.发明授权Nonvolatile semiconductor memory device and method of erasing data of nonvolatile semiconductor memory device 有权非易失性半导体存储器件和擦除非易失性半导体存储器件的数据的方法公开(公告)号：US06330192B1
公开(公告)日：2001-12-11
申请号：US09676758
申请日：2000-10-02
IPC分类号： G11C1600
CPC分类号： G11C16/3409 , G11C16/3404
摘要： Operations of applying an erase pulse and further performing block program before erasure are executed in steps S2 and S3 before applying the erase pulse on a block by block basis. This narrows the distribution width of the threshold voltage, and reduces the number of the memory transistors to be subjected to over-erase verify so that a total erasing time of data of a flash memory can be reduced.
摘要翻译： 在擦除脉冲之前在步骤S2和S3中执行擦除脉冲之前的施加擦除脉冲和进一步执行块程序的操作，然后逐块地应用擦除脉冲。 这会使阈值电压的分布宽度变窄，并且减少要进行过擦除验证的存储晶体管的数量，从而可以减少闪速存储器的数据的总擦除时间。
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3.发明授权Nonvolatile semiconductor memory device and method of erasing data of nonvolatile semiconductor memory device 有权非易失性半导体存储器件和擦除非易失性半导体存储器件的数据的方法公开(公告)号：US06567316B1
公开(公告)日：2003-05-20
申请号：US09985013
申请日：2001-11-01
IPC分类号： G11C1600
CPC分类号： G11C16/3409 , G11C16/3404
摘要： Operations of applying an erase pulse and further performing block program before erasure are executed in steps S2 and S3 before applying the erase pulse on a block by block basis. This narrows the distribution width of the threshold voltage, and reduces the number of the memory transistors to be subjected to over-erase verify so that a total erasing time of data of a flash memory can be reduced.
摘要翻译： 在擦除脉冲之前在步骤S2和S3中执行擦除脉冲之前的施加擦除脉冲和进一步执行块程序的操作，然后逐块地应用擦除脉冲。 这会使阈值电压的分布宽度变窄，并且减少要进行过擦除验证的存储晶体管的数量，从而可以减少闪速存储器的数据的总擦除时间。
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4.发明授权SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY TESTED EVEN WHEN THE NUMBER OF SEMICONDUCTOR MEMORY DEVICES IS LARGE AND SEMICONDUCTOR WAFER ON WHICH THE SEMICONDUCTOR MEMORY DEVICES ARE FORMED 失效半导体存储器件的半导体存储器件，即使半导体存储器件的数量大于半导体存储器件形成的半导体器件，也可以同时测试公开(公告)号：US06473345B2
公开(公告)日：2002-10-29
申请号：US09909786
申请日：2001-07-23
IPC分类号： G11C700
CPC分类号： G11C29/48 , G11C29/006
摘要： At the time of writing data, a tester outputs a chip enable signal /CE of the L level and selection signals of the L level to simultaneously make semiconductor memory devices active. At the time of reading data, the tester outputs the chip enable signal of the L level to the semiconductor memory devices, and selectively switches the logic level of a selection signal to be outputted to some semiconductor memory devices and that of the selection signal to be outputted to the other semiconductor memory devices to the L level. In such a manner, a number of semiconductor memory devices can be tested without increasing the number of pins of the tester.
摘要翻译： 在写入数据时，测试仪输出L电平的芯片使能信号/ CE和L电平的选择信号，以同时使半导体存储器件处于活动状态。 在读取数据时，测试仪将半导体存储器件的L电平的芯片使能信号输出到选择信号的选择信号的逻辑电平，并将选择信号的逻辑电平切换到一些半导体存储器件 输出到其他半导体存储器件到L电平。 以这种方式，可以在不增加测试器的引脚数的情况下测试多个半导体存储器件。
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公开(公告)号：US06515908B2
公开(公告)日：2003-02-04
申请号：US09845300
申请日：2001-05-01
IPC分类号： G11C1606
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.
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6.发明授权Nonvolatile semiconductor memory device capable of high speed generation of rewrite voltage 失效能够高速产生重写电压的非易失性半导体存储器件公开(公告)号：US06385086B1
公开(公告)日：2002-05-07
申请号：US09735618
申请日：2000-12-14
申请人： Masaaki Mihara , Yoshikazu Miyawaki , Shinji Kawai
发明人： Masaaki Mihara , Yoshikazu Miyawaki , Shinji Kawai
IPC分类号： G11C1604
摘要： A voltage generation portion includes a voltage amplifier circuit, receiving a boosted potential VPP generated by a charge pump circuit to output an output potential Vout equal to a standard potential VIN. Output potentials Vout are distributed as voltages for rewriting and erasing on a flash memory via distributor. The output potential Vout can be changed faster than the boosted potential VPP generated by the charge pump circuit does.
摘要翻译： 电压产生部分包括电压放大器电路，接收由电荷泵电路产生的升压电位VPP，以输出等于标准电位VIN的输出电位Vout。 输出电位Vout分配为经由分配器在闪速存储器上重写和擦除的电压。 输出电位Vout可以比由电荷泵电路产生的升压电位VPP更快地改变。
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7.发明授权Nonvolatile semiconductor memory device capable of reducing memory array area 有权能够减少存储器阵列区域的非易失性半导体存储器件公开(公告)号：US06243292B1
公开(公告)日：2001-06-05
申请号：US09613691
申请日：2000-07-10
IPC分类号： G11C700
CPC分类号： H01L27/115 , G11C16/26 , G11C16/30 , G11C16/3436
摘要： A memory cell array is divided into a plurality of memory cell blocks each collectively subjected to an erasing operation as a unit. A P well regions for memory cell transistors and an N well region for electrically separating the P well regions are provided. Select transistors are formed in the same P well region as the memory cell transistor connected to the corresponding sub bit line of P well regions.
摘要翻译： 存储单元阵列被分成以共同作为单位进行擦除操作的多个存储单元块。 提供存储单元晶体管的P阱区和用于电分离P阱区的N阱区。 选择晶体管形成在与连接到P阱区域的对应子位线的存储单元晶体管相同的P阱区域中。
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8.发明授权Nonvolatile semiconductor memory device and method of erasing stored data thereof 失效非易失性半导体存储器件及其存储数据的擦除方法
公开(公告)号：US5563824A
公开(公告)日：1996-10-08
申请号：US357697
申请日：1994-12-16
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： A source line of a memory array included in a flash memory is set to a 3V potential by a source line circuit, a power supply voltage of 6V is applied to a sense amplifier, and 3V is applied as the ground potential. After the setting of such potential conditions, reading of the memory array is performed. When current flows to the memory cells as a result of reading, it means that the memory cell has been erased. If the current does not flows through the memory cell, erasure pulse is applied again and every memory cell is verified.
摘要翻译： 包含在闪速存储器中的存储器阵列的源极线通过源极线电路设置为3V电位，6V的电源电压被施加到读出放大器，并且施加3V作为接地电位。 在设置这样的潜在条件之后，执行存储器阵列的读取。 当电流由于读取而流向存储单元时，这意味着存储单元已被擦除。 如果电流不流过存储单元，则再次施加擦除脉冲，并且验证每个存储单元。
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公开(公告)号：US20050083737A1
公开(公告)日：2005-04-21
申请号：US10962600
申请日：2004-10-13
CPC分类号： G11C16/10 , G11C11/5628
摘要： In the present flash memory a threshold voltage of a memory transistor to which data is written is detected and the detected value is used to set an initial value of a pulse voltage of a write pulse signal, and whenever the write pulse signal is applied, the pulse voltage is increased by a step voltage. The memory transistor's drain current and the threshold voltage's variation can be smaller than when a fixed pulse voltage is applied, as conventional.
摘要翻译： 在本闪速存储器中，检测写入数据的存储晶体管的阈值电压，并且使用检测值来设定写入脉冲信号的脉冲电压的初始值，并且每当施加写入脉冲信号时， 脉冲电压由步进电压增加。 存储晶体管的漏极电流和阈值电压的变化可以比常规的施加固定的脉冲电压时的小。
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公开(公告)号：US06483748B2
公开(公告)日：2002-11-19
申请号：US09729415
申请日：2000-12-05
IPC分类号： G11C1604
CPC分类号： G11C7/1069 , G11C7/06 , G11C7/1051 , G11C7/1078 , G11C16/26
摘要： An external read sense amplifier for reading out a data to an outside and an internal verify sense amplifier for reading out a data for an internal operation are provided, separately from each other, to a plurality of banks. Preferably, an internal verify sense amplifier is provided for each prescribed number of memory blocks. There is provided a nonvolatile semiconductor memory device with a background operation function, having a reduced chip occupancy area.
摘要翻译： 将用于向外部读出数据的外部读取读出放大器和用于读出用于内部操作的数据的内部校验读出放大器彼此分开地提供给多个存储体。 优选地，为每个规定数量的存储块提供内部校验读出放大器。 提供了具有背景操作功能的非易失性半导体存储器件，具有减小的芯片占用面积。
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