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    Nonvolatile semiconductor memory device with a row redundancy circuit
    2.
    发明授权
    Nonvolatile semiconductor memory device with a row redundancy circuit 失效
    具有行冗余电路的非易失性半导体存储器件

    公开(公告)号：US5602778A

    公开(公告)日：1997-02-11

    申请号：US468393

    申请日：1995-06-06

    申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C11/34

    CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

    摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

    摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

    Nonvolatile semiconductor memory device with a row redundancy circuit
    3.
    发明授权
    Nonvolatile semiconductor memory device with a row redundancy circuit 失效
    具有行冗余电路的非易失性半导体存储器件

    公开(公告)号：US5548557A

    公开(公告)日：1996-08-20

    申请号：US179731

    申请日：1994-01-11

    申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

    摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

    摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

    Nonvolatile semiconductor memory device
    4.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5347490A

    公开(公告)日：1994-09-13

    申请号：US711532

    申请日：1991-06-10

    申请人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi

    发明人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi

    IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/16 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  G11C11/34

    CPC分类号： G11C5/147 ,  G11C16/16 ,  G11C16/30

    摘要： Disclosed is a flash EEPROM including a voltage lowering circuit therein for lowering an externally applied high voltage serving as a source of an erase pulse to a predetermined voltage in a range in which a tunnel phenomenon sufficiently occurs in memory cells. The voltage lowered by the voltage lowering circuit is converted into a pulse of a small width, and the converted pulse is then applied as an erase pulse to the memory cells. A flash EEPROM including a memory cell array divided into first and second blocks is also disclosed. An erase pulse applying circuit for applying the voltage lowered by the voltage lowering circuit as an erase pulse to the memory cells, and an erase verify circuit for erase verifying are provided for each of the first and second blocks. The erase pulse applying circuit and the erase verify circuit corresponding to the first block and the ones corresponding to the second block are configured to operate independently.

    摘要翻译： 公开了一种闪速EEPROM，其包括其中在存储单元中充分发生隧道现象的范围内将用作擦除脉冲源的外部施加的高电压降低到预定电压的电压降低电路。 由降压电路降低的电压被转换为宽度较小的脉冲，然后将转换的脉冲作为擦除脉冲施加到存储单元。 还公开了一种包括分为第一和第二块的存储单元阵列的闪存EEPROM。 提供了用于将由降压电路降低的电压作为擦除脉冲施加到存储单元的擦除脉冲施加电路，以及用于擦除验证的擦除验证电路用于第一和第二块中的每一个。 擦除脉冲施加电路和对应于第一块的擦除验证电路和对应于第二块的擦除验证电路被配置为独立地操作。

    Semiconductor integrated circuit having multiple self-test functions and operating method therefor
    5.
    发明授权
    Semiconductor integrated circuit having multiple self-test functions and operating method therefor 失效
    具有多个自检功能的半导体集成电路及其操作方法

    公开(公告)号：US4970727A

    公开(公告)日：1990-11-13

    申请号：US263118

    申请日：1988-10-27

    申请人： Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Takeshi Nakayama ,  Kazuo Kobayashi ,  Yasushi Terada

    发明人： Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Takeshi Nakayama ,  Kazuo Kobayashi ,  Yasushi Terada

    IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G11C16/02 ,  G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46

    CPC分类号： G11C29/46 ,  G01R31/31701

    摘要： In a semiconductor integrated circuit such as a semiconductor memory device capable of operating in a special mode in addition to a standard operation mode, a high voltage detection circuit 10 detects a high voltage applied to one of control signal input terminals CS and outputs a detection signal HV to a special mode circuit 14. The special mode circuit 14 outputs a switch signal CO to a switching circuit 11 in response to the detection signal HV. The switching circuit 11 connects an input/output buffer 7 to a latch circuit 12 in response to the switch signal CO. A special mode code MC is applied to input/output terminals DT and transmitted to the latch circuit 12 through the switching circuit 11. A special mode decoder 13 decodes the special mode code MC which has been latched by the latch circuit 12 and outputs a signal for specifying the special mode to a control circuit 8. Operation in the special mode specified by the control circuit 8 is executed. By detecting a confirmation signal CS applied to one of the control signal input terminals CS during the execution of the special mode, the special mode code MC which has been already latched by the latch circuit 12 can be outputted from the input/output terminals DT.

    摘要翻译： 在除了标准工作模式之外能够以特殊模式工作的半导体存储器件的半导体集成电路中，高电压检测电路10检测施加到控制信号输入端子CS之一的高电压，并输出检测信号 HV到特殊模式电路14.特殊模式电路14响应于检测信号HV将开关信号CO输出到开关电路11。 开关电路11响应于开关信号CO将输入/输出缓冲器7连接到锁存电路12.特殊模式代码MC被施加到输入/输出端子DT，并通过开关电路11发送到锁存电路12。 特殊模式解码器13解码由锁存电路12锁存的特殊模式代码MC，并将用于指定特殊模式的信号输出到控制电路8.执行由控制电路8指定的特殊模式中的操作。 通过检测在特殊模式执行期间施加到控制信号输入端子CS之一的确认信号CS，可以从输入/输出端子DT输出已被锁存电路12锁存的特殊模式代码MC。

    Non-volatile semiconductor memory device
    9.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5283758A

    公开(公告)日：1994-02-01

    申请号：US794708

    申请日：1991-11-20

    申请人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

    发明人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

    IPC分类号： G11C7/18 ,  G11C16/04 ,  G11C16/16 ,  G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0425 ,  G11C16/0491 ,  G11C7/18

    摘要： A plurality of memory cell transistors having floating gates are disposed in a matrix in the direction of row and column to form a memory cell array. The memory cell array is divided into a plurality of sectors for every predetermined row. In each sector, sector selecting transistors and sub bit lines are provided, so that erasing and programming can be made for each sector. Therefore, total erasing for sector becomes possible, and since no voltage is applied to sub bit lines and word lines of non-selected sectors, the number of operations of preventing writing into non-selected memory cells is as many as the word lines included in one sector.

    摘要翻译： 具有浮动栅极的多个存储单元晶体管以行和列的方向设置在矩阵中以形成存储单元阵列。 存储单元阵列被划分成用于每个预定行的多个扇区。 在每个扇区中，提供扇区选择晶体管和子位线，从而可以对每个扇区进行擦除和编程。 因此，扇区的全部擦除成为可能，并且由于没有电压施加到非选择扇区的子位线和字线，所以防止写入未选择的存储单元的操作次数与包括在 一个部门。