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1.发明授权Nonvolatile semiconductor memory device and method of erasing stored data thereof 失效非易失性半导体存储器件及其存储数据的擦除方法
公开(公告)号：US5563824A
公开(公告)日：1996-10-08
申请号：US357697
申请日：1994-12-16
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： A source line of a memory array included in a flash memory is set to a 3V potential by a source line circuit, a power supply voltage of 6V is applied to a sense amplifier, and 3V is applied as the ground potential. After the setting of such potential conditions, reading of the memory array is performed. When current flows to the memory cells as a result of reading, it means that the memory cell has been erased. If the current does not flows through the memory cell, erasure pulse is applied again and every memory cell is verified.
摘要翻译： 包含在闪速存储器中的存储器阵列的源极线通过源极线电路设置为3V电位，6V的电源电压被施加到读出放大器，并且施加3V作为接地电位。 在设置这样的潜在条件之后，执行存储器阵列的读取。 当电流由于读取而流向存储单元时，这意味着存储单元已被擦除。 如果电流不流过存储单元，则再次施加擦除脉冲，并且验证每个存储单元。
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2.发明授权Nonvolatile semiconductor memory device capable of high speed generation of rewrite voltage 失效能够高速产生重写电压的非易失性半导体存储器件公开(公告)号：US06385086B1
公开(公告)日：2002-05-07
申请号：US09735618
申请日：2000-12-14
申请人： Masaaki Mihara , Yoshikazu Miyawaki , Shinji Kawai
发明人： Masaaki Mihara , Yoshikazu Miyawaki , Shinji Kawai
IPC分类号： G11C1604
摘要： A voltage generation portion includes a voltage amplifier circuit, receiving a boosted potential VPP generated by a charge pump circuit to output an output potential Vout equal to a standard potential VIN. Output potentials Vout are distributed as voltages for rewriting and erasing on a flash memory via distributor. The output potential Vout can be changed faster than the boosted potential VPP generated by the charge pump circuit does.
摘要翻译： 电压产生部分包括电压放大器电路，接收由电荷泵电路产生的升压电位VPP，以输出等于标准电位VIN的输出电位Vout。 输出电位Vout分配为经由分配器在闪速存储器上重写和擦除的电压。 输出电位Vout可以比由电荷泵电路产生的升压电位VPP更快地改变。
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3.发明授权Semiconductor integrated circuit device with adjustable high voltage detection circuit 失效具有可调高压检测电路的半导体集成电路器件
公开(公告)号：US6008674A
公开(公告)日：1999-12-28
申请号：US927796
申请日：1997-09-11
摘要： A semiconductor integrated circuit device with a high voltage detection circuit comprises a high voltage step-down circuit for stepping down a high voltage input and outputting the stepped-down voltage, a reference voltage generator for generating plural reference voltages, a reference voltage selector for selecting one of the plural reference voltages, a high voltage detection circuit for comparing the stepped down voltage with the selected reference voltage to detect a high voltage and a control circuit for controlling the voltage drop of the high voltage and selection of the plural reference voltages to set the high voltage to be detected by the high voltage detector. There is also disclosed semiconductor integrated circuit having a high voltage step-down circuit for outputting plural stepped-down voltages having a fine tuner for fine-tuning each of the plural stepped-down voltages wherein a stepped-down voltage having been tuned finely is compared with a reference voltage given by a reference voltage generator.
摘要翻译： 具有高电压检测电路的半导体集成电路装置包括用于降压高压输入并输出降压的高压降压电路，用于产生多个参考电压的参考电压发生器，用于选择的参考电压选择器 多个参考电压中的一个，用于将降压电压与所选择的参考电压进行比较以检测高电压的高电压检测电路，以及用于控制高电压的电压降和选择多个参考电压的控制电路以设置 由高电压检测器检测的高电压。 还公开了一种具有高压降压电路的半导体集成电路，用于输出具有微调整器的多个降压电压，用于微调多个降压电压中的每一个，其中比较精调的降压电压 具有由参考电压发生器给出的参考电压。
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公开(公告)号：US5959890A
公开(公告)日：1999-09-28
申请号：US27194
申请日：1998-02-20
摘要： A non-volatile semiconductor memory device comprises a bit line 402, a plurality of word lines 401 arranged to cross the bit line 402, a plurality of non-volatile memory cells 404 which are disposed at the crossing points of the bit line 402 and the word lines 401 and which have a drain 404a connected to the bit line 402 and a control gate 404f connected to the corresponding word line 401, anda word line potential applying means 300, 500 wherein in an ordinary reading mode, a selective potential is applied to a word line 401 selected from the plurality of word lines, while a non-selective potential, which is lower than the selective potential, is applied to unselected word lines 401 in response to an address signal, and in a prescribed mode, the selective potential is applied to a word line 401 selected from the plurality of word lines, while a prescribed potential, which is lower than the non-selective potential, is applied to the unselected word lines in response to an address signal.
摘要翻译： 非易失性半导体存储器件包括位线402，布置成穿过位线402的多个字线401，多个非易失性存储器单元404，其设置在位线402和 字线401并且具有连接到位线402的漏极404a和连接到对应字线401的控制栅极404f以及字线电位施加装置300,500，其中在普通读取模式中施加选择电位 到选自多个字线的字线401，而低于选择电位的非选择性电位响应于地址信号被施加到未选字线401，并且在规定模式中，选择性地选择 电位被施加到从多个字线中选择的字线401，而低于非选择电位的规定电位响应于地址信号被施加到未选字线 l。
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5.发明授权
公开(公告)号：US5548557A
公开(公告)日：1996-08-20
申请号：US179731
申请日：1994-01-11
申请人： Tomoshi Futatsuya , Masaaki Mihara , Yasushi Terada , Takeshi Nakayama , Yoshikazu Miyawaki , Shinichi Kobayashi , Minoru Ohkawa
发明人： Tomoshi Futatsuya , Masaaki Mihara , Yasushi Terada , Takeshi Nakayama , Yoshikazu Miyawaki , Shinichi Kobayashi , Minoru Ohkawa
CPC分类号： G11C29/804 , G11C16/08 , G11C29/82 , G11C29/848
摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.
摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。
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6.发明授权High voltage generating device having variable boosting capability according to magnitude of load 失效根据负载大小，具有可变升压能力的高压发生装置
公开(公告)号：US5940283A
公开(公告)日：1999-08-17
申请号：US882344
申请日：1997-06-25
申请人： Masaaki Mihara , Yoshikazu Miyawaki
发明人： Masaaki Mihara , Yoshikazu Miyawaki
CPC分类号： H02M3/073
摘要： A high voltage generating device includes a charge pump generating high voltage by boosting a power supply voltage and supplying it to a load, a timer measuring activation time of the charge pump and outputting a signal after a prescribed time period, an A-D converter converting an output voltage of the charge pump into a digital value in response to the signal and outputting four bit binary data, and a current limiting circuit including four P channel MOS transistors connected in parallel between a power supply node and a drain of an N channel MOS transistor which has a gate receiving the digital value output from the A-D converter.
摘要翻译： 高电压产生装置包括通过升高电源电压并将其提供给负载来产生高电压的电荷泵，定时器测量电荷泵的激活时间并在规定的时间段之后输出信号，AD转换器将输出 电荷泵的电压响应于信号而变为数字值并输出四位二进制数据;以及限流电路，包括并联连接在N沟道MOS晶体管的电源节点和漏极之间的四个P沟道MOS晶体管， 具有从AD转换器输出的数字值的门。
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7.发明授权
公开(公告)号：US5602778A
公开(公告)日：1997-02-11
申请号：US468393
申请日：1995-06-06
申请人： Tomoshi Futatsuya , Masaaki Mihara , Yasushi Terada , Takeshi Nakayama , Yoshikazu Miyawaki , Shinichi Kobayashi , Minoru Ohkawa
发明人： Tomoshi Futatsuya , Masaaki Mihara , Yasushi Terada , Takeshi Nakayama , Yoshikazu Miyawaki , Shinichi Kobayashi , Minoru Ohkawa
CPC分类号： G11C29/804 , G11C16/08 , G11C29/82 , G11C29/848
摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.
摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。
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公开(公告)号：US06560164B2
公开(公告)日：2003-05-06
申请号：US09977275
申请日：2001-10-16
申请人： Shinji Kawai , Masaaki Mihara
发明人： Shinji Kawai , Masaaki Mihara
IPC分类号： G11C800
摘要： A temperature dependency of an internal clock signal generated by an internal clock generating circuit is effectively reduced. A temperature detecting circuit is provided to a variable clock generator for generating the internal clock signal and an oscillating cycle period of the variable clock generator is altered according to a detection signal of the temperature detecting circuit. A cycle of the internal clock signal is altered and a temperature dependency of the internal clock signal is effectively compensated for.
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公开(公告)号：US08017994B2
公开(公告)日：2011-09-13
申请号：US12499220
申请日：2009-07-08
IPC分类号： H01L29/792
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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公开(公告)号：US20090310409A1
公开(公告)日：2009-12-17
申请号：US12499220
申请日：2009-07-08
IPC分类号： G11C16/04 , H01L29/792 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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