公开(公告)号：US20100164607A1

公开(公告)日：2010-07-01

申请号：US12647259

申请日：2009-12-24

申请人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

发明人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

IPC分类号： G05F1/10

CPC分类号： G05F3/205 ,  G05F1/46

摘要： To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.

摘要翻译： 为了提供一种半导体器件，包括：形成在半导体衬底中并具有要调节的阈值电压的MOS晶体管，MOS晶体管的复制晶体管，监视电路监视当复制晶体管流过具有 给定的设计值，负电压泵浦电路基于监控电路的输出产生MOS晶体管的衬底电压，并且限制电路定义负电压抽运电路的操作，而不管监视的监视结果如何 电路，响应于相对于预定值的衬底电压的过量。

公开(公告)号：US08217712B2

公开(公告)日：2012-07-10

申请号：US12647259

申请日：2009-12-24

申请人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

发明人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G05F3/205 ,  G05F1/46

摘要： To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.

摘要翻译： 为了提供一种半导体器件，包括：形成在半导体衬底中并具有要调节的阈值电压的MOS晶体管，MOS晶体管的复制晶体管，监视电路监视当复制晶体管流过具有 给定的设计值，负电压泵浦电路基于监控电路的输出产生MOS晶体管的衬底电压，并且限制电路定义负电压抽运电路的操作，而不管监视的监视结果如何 电路，响应于相对于预定值的衬底电压的过量。

公开(公告)号：US08773195B2

公开(公告)日：2014-07-08

申请号：US12662044

申请日：2010-03-29

申请人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

发明人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

IPC分类号： H03K3/01 ,  G05F3/02

CPC分类号： G05F1/463 ,  G05F1/462 ,  G05F3/205 ,  G05F3/242 ,  G11C5/147

摘要： A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller.

摘要翻译： 半导体器件防止互补场效应晶体管的导通电流随着环境温度的变化而变化。 半导体器件包括：产生CMOS的电源电压的缓冲电路; 第一复制晶体管，其是形成CMOS的p沟道MOS晶体管的复制品，并且是二极管连接的; 第二复制晶体管，其是形成CMOS的n沟道MOS晶体管的复制品，并且是二极管连接的; 以及电压控制器，其控制复制晶体管的阳极和阴极之间的电压，使得流入复制晶体管的电流的电流值等于给定的目标值。 在该半导体器件中，缓冲电路产生电源电压，目标电压是由电压控制器控制的电压。

公开(公告)号：US08222952B2

公开(公告)日：2012-07-17

申请号：US12662038

申请日：2010-03-29

申请人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

发明人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

IPC分类号： H03K3/01

CPC分类号： H03K19/00361 ,  H03K19/0008 ,  H03K2217/0018

摘要： A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.

摘要翻译： 半导体器件防止互补场效应晶体管的截止电流随着环境温度的变化而变化。 半导体器件包括：衬底电压产生电路，其产生形成CMOS的n沟道MOS晶体管的衬底电压; 复制晶体管，其是n沟道MOS晶体管的复制品，并且是二极管连接的; 以及在复制晶体管的阳极和阴极之间施加预定电压值的电压的施加电压器。 在该半导体器件中，复制晶体管的衬底电压是由衬底电压产生电路产生的衬底电压。 衬底电压产生电路控制要产生的衬底电压，使得流入复制晶体管的电流的电流值等于给定的目标值。

公开(公告)号：US20100244936A1

公开(公告)日：2010-09-30

申请号：US12662038

申请日：2010-03-29

申请人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

发明人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

IPC分类号： G05F1/10

CPC分类号： H03K19/00361 ,  H03K19/0008 ,  H03K2217/0018

摘要： A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.

摘要翻译： 半导体器件防止互补场效应晶体管的截止电流随着环境温度的变化而变化。 半导体器件包括：衬底电压产生电路，其产生形成CMOS的n沟道MOS晶体管的衬底电压; 复制晶体管，其是n沟道MOS晶体管的复制品，并且是二极管连接的; 以及在复制晶体管的阳极和阴极之间施加预定电压值的电压的施加电压器。 在该半导体器件中，复制晶体管的衬底电压是由衬底电压产生电路产生的衬底电压。 衬底电压产生电路控制要产生的衬底电压，使得流入复制晶体管的电流的电流值等于给定的目标值。

公开(公告)号：US20100244908A1

公开(公告)日：2010-09-30

申请号：US12662044

申请日：2010-03-29

申请人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

发明人： Shinichi Miyatake ,  Seiji Narui ,  Hitoshi Tanaka

IPC分类号： G05F3/16

CPC分类号： G05F1/463 ,  G05F1/462 ,  G05F3/205 ,  G05F3/242 ,  G11C5/147

摘要： A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller.

摘要翻译： 半导体器件防止互补场效应晶体管的导通电流随着环境温度的变化而变化。 半导体器件包括：产生CMOS的电源电压的缓冲电路; 第一复制晶体管，其是形成CMOS的p沟道MOS晶体管的复制品，并且是二极管连接的; 第二复制晶体管，其是形成CMOS的n沟道MOS晶体管的复制品，并且是二极管连接的; 以及电压控制器，其控制复制晶体管的阳极和阴极之间的电压，使得流入复制晶体管的电流的电流值等于给定的目标值。 在该半导体器件中，缓冲电路产生电源电压，目标电压是由电压控制器控制的电压。

公开(公告)号：US5905685A

公开(公告)日：1999-05-18

申请号：US951734

申请日：1997-10-15

申请人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

发明人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C11/408 ,  G11C11/4087

摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.

摘要翻译： 在具有存储单元阵列的动态RAM中，其中动态存储单元布置在字线和一对位线中的一个位线之间的交叉点处，对应于电源电压的选择电平信号和对应于 低于电路接地电位的负电位被提供给字线。 通过由电路接地电位进行工作的读出放大器对一对位线读取的存储单元的信号和通过将电源电压降低等于地址选择MOSFET的阈值电压的量而形成的内部电压被放大。 动态RAM具有接收电源电压和电路接地电位的振荡器，以及接收由振荡器产生的振荡脉冲以产生负电位的电路。

公开(公告)号：US06201728B1

公开(公告)日：2001-03-13

申请号：US09101009

申请日：1999-02-08

申请人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

发明人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

IPC分类号： G11C1124

CPC分类号： G11C11/4091 ,  G11C7/065 ,  H01L27/10805

摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.

摘要翻译： 产生相对于电源电压具有差异的第一内部电压，该差基本上等于动态存储单元的地址选择MOSFET的阈值电压。 第一电压作为其高级侧的工作电压被提供给读出放大器。 产生相对于电路接地电位具有预定差异的第二内部电压。 第二电压作为低电平侧的工作电压提供给读出放大器。 通过写放大器产生具有对应于第一内部电压的高电平和对应于第二内部电压的低电平的写入信号，以将其传送到连接到动态存储单元的一对互补数据线。 高电平，例如表示选择电平和低电平的电源电压，例如指示非选择电平的电路接地电平被提供给连接到动态存储器单元的字线。

公开(公告)号：US06411543B1

公开(公告)日：2002-06-25

申请号：US09755170

申请日：2001-01-08

申请人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

发明人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

IPC分类号： G11C1124

摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.

公开(公告)号：US06992343B2

公开(公告)日：2006-01-31

申请号：US10975494

申请日：2004-10-29

申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/比特方法的DRAM具有采用单交叉6F 单元的双单元结构，其结构是：将存储单元布置在与 位线对和字线之间的交点; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。 此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。