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    Semiconductor device
    1.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08467217B2

    公开(公告)日：2013-06-18

    申请号：US12929896

    申请日：2011-02-23

    申请人： Shinichi Takayama ,  Kazuhiko Kajigaya ,  Akira Kotabe ,  Satoru Akiyama ,  Tomonori Sekiguchi

    发明人： Shinichi Takayama ,  Kazuhiko Kajigaya ,  Akira Kotabe ,  Satoru Akiyama ,  Tomonori Sekiguchi

    IPC分类号： G11C5/06 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/02 ,  G11C11/4091 ,  G11C11/4097 ,  G11C29/04 ,  G11C2207/002 ,  G11C2207/005

    摘要： The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.

    摘要翻译： 半导体器件包括第一和第二存储器单元，连接到第一/第二存储器单元的第一和第二位线，连接到第二位线的第一和第二放大器，共同连接到第一/第二放大器的本地输入/输出线， 连接在第一/第二放大器和本地输入/输出线之间的第一和第二本地列开关，连接在第二放大器和本地输入/输出线之间的第二本地列开关，列选择线，连接的第一全局列开关 在列选择线和第一本地列开关之间并响应于第一选择信号控制它们之间的连接;以及连接在列选择线和第二本地列开关之间的第二全局列开关，并且响应于 第一选择信号。

    Semiconductor device
    2.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20110205820A1

    公开(公告)日：2011-08-25

    申请号：US12929896

    申请日：2011-02-23

    申请人： Shinichi Takayama ,  Kazuhiko Kajigaya ,  Akira Kotabe ,  Satoru Akiyama ,  Tomonori Sekiguchi

    发明人： Shinichi Takayama ,  Kazuhiko Kajigaya ,  Akira Kotabe ,  Satoru Akiyama ,  Tomonori Sekiguchi

    IPC分类号： G11C29/04 ,  G11C7/06

    CPC分类号： G11C29/02 ,  G11C11/4091 ,  G11C11/4097 ,  G11C29/04 ,  G11C2207/002 ,  G11C2207/005

    摘要： The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.

    摘要翻译： 半导体器件包括第一和第二存储器单元，连接到第一/第二存储器单元的第一和第二位线，连接到第二位线的第一和第二放大器，共同连接到第一/第二放大器的本地输入/输出线， 连接在第一/第二放大器和本地输入/输出线之间的第一和第二本地列开关，连接在第二放大器和本地输入/输出线之间的第二本地列开关，列选择线，连接的第一全局列开关 在列选择线和第一本地列开关之间并响应于第一选择信号控制它们之间的连接;以及连接在列选择线和第二本地列开关之间的第二全局列开关，并且响应于 第一选择信号。

    Timing control circuit, timing generation system, timing control method and semiconductor memory device
    6.
    发明授权
    Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
    定时控制电路，定时生成系统，定时控制方法和半导体存储器件

    公开(公告)号：US07750712B2

    公开(公告)日：2010-07-06

    申请号：US12314207

    申请日：2008-12-05

    申请人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

    发明人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

    IPC分类号： H03H11/26

    CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C19/00 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03K2005/00241

    摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.

    摘要翻译： 定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟 延迟元件 定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。 粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。 精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。 定时信号延迟的变化减小。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07505299B2

    公开(公告)日：2009-03-17

    申请号：US11976531

    申请日：2007-10-25

    申请人： Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Tomonori Sekiguchi ,  Kazuhiko Kajigaya

    发明人： Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Tomonori Sekiguchi ,  Kazuhiko Kajigaya

    IPC分类号： G11C5/06 ,  G11C11/24 ,  G11C7/02 ,  G11C8/00

    CPC分类号： G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10873

    摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.

    摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

    Semiconductor memory device
    8.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060158924A1

    公开(公告)日：2006-07-20

    申请号：US11280170

    申请日：2005-11-17

    申请人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10882

    摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.

    摘要翻译： 从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压 晶体管经由存储单元晶体管写入电容器的存储节点。 此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且 根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

    Design methodology and manufacturing method for semiconductor memory
    9.
    发明申请
    Design methodology and manufacturing method for semiconductor memory 审中-公开
    半导体存储器的设计方法和制造方法

    公开(公告)号：US20060142988A1

    公开(公告)日：2006-06-29

    申请号：US11318431

    申请日：2005-12-28

    申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Takayuki Kawahara ,  Kazuhiko Kajigaya

    发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Takayuki Kawahara ,  Kazuhiko Kajigaya

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G06F2217/10 ,  G06F2217/78

    摘要： A manufacturing method for semiconductor memory and a semiconductor design device, which can facilitate design and reduce a period of time required for the design, are provided. For example, when a designed memory array is verified, a read-out signal of a memory cell formulated by functions of respective parameters having various distributions is used. A value of the read-out signal is calculated by using a value extracted randomly from the distribution for each kind of parameter. Quality of the memory cell is determined from a calculated result. Calculation of the value of the read-out signal and determination of the quality of the memory cell are carried out to a great number of memory cells the memory array has. The total number of failed bits and the like obtained from these is used as an evaluation criterion.

    摘要翻译： 提供一种半导体存储器和半导体设计装置的制造方法，其可以促进设计并减少设计所需的时间。 例如，当设计的存储器阵列被验证时，使用由具有各种分布的各个参数的功能所制定的存储器单元的读出信号。 通过使用从各种参数的分布中随机提取的值来计算读出信号的值。 从计算结果确定存储单元的质量。 对存储器阵列具有的大量存储单元执行读出信号的值的计算和存储单元的质量的确定。 将从这些获得的故障比特等的总数用作评估标准。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 失效

    公开(公告)号：US08472273B2

    公开(公告)日：2013-06-25

    申请号：US13117374

    申请日：2011-05-27

    申请人： Shinichi Takayama ,  Akira Kotabe ,  Kiyoo Itoh ,  Tomonori Sekiguchi

    发明人： Shinichi Takayama ,  Akira Kotabe ,  Kiyoo Itoh ,  Tomonori Sekiguchi

    IPC分类号： G11C7/02

    CPC分类号： G11C7/08 ,  G11C11/4091 ,  G11C11/4094

    摘要： A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.