公开(公告)号：US20120021588A1

公开(公告)日：2012-01-26

申请号：US13184591

申请日：2011-07-18

申请人： Shinya HASEGAWA ,  Atsuo ISOBE ,  Motomu KURATA

发明人： Shinya HASEGAWA ,  Atsuo ISOBE ,  Motomu KURATA

IPC分类号： H01L21/265

CPC分类号： H01L21/76254

摘要： One object is to provide excellent electric characteristics of an end portion of a single crystal semiconductor layer having a tapered shape. An embrittled region is formed in a single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with accelerated ions. Then, the single crystal semiconductor substrate and a base substrate are bonded to each other with an insulating film interposed therebetween and a first single crystal semiconductor layer is formed over the base substrate with the insulating film interposed therebetween by separating the single crystal semiconductor substrate at the embrittled region. After that, a second single crystal semiconductor layer having a tapered end portion is formed by performing dry etching on the first single crystal semiconductor layer, and etching is performed on the end portion of the second single crystal semiconductor layer in a state where a potential on the base substrate side is a ground potential.

摘要翻译： 一个目的是提供具有锥形形状的单晶半导体层的端部的优异的电特性。 通过用加速离子照射单晶半导体衬底，在单晶半导体衬底中形成脆化区域。 然后，将单晶半导体衬底和基底衬底彼此接合，并且隔着绝缘膜在基底衬底上形成第一单晶半导体层，通过在第一单晶半导体衬底上分离单晶半导体衬底 脆弱的地区。 之后，通过在第一单晶半导体层上进行干蚀刻来形成具有锥形端部的第二单晶半导体层，并且在第二单晶半导体层的端部进行蚀刻， 基底侧是接地电位。

公开(公告)号：US20090029514A1

公开(公告)日：2009-01-29

申请号：US12178356

申请日：2008-07-23

申请人： Tomokazu YOKOI ,  Atsuo ISOBE ,  Motomu KURATA ,  Takeshi SHICHI ,  Daisuke OHGARANE ,  Takashi SHINGU

发明人： Tomokazu YOKOI ,  Atsuo ISOBE ,  Motomu KURATA ,  Takeshi SHICHI ,  Daisuke OHGARANE ,  Takashi SHINGU

IPC分类号： H01L21/336

CPC分类号： H01L29/66765

摘要： A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).

摘要翻译： 一种制造半导体器件的方法，通过该方法可以以简单的方法制造具有改善的S值的底栅极薄膜晶体管和具有比源极区和漏极区更小的厚度的沟道形成区。 在对应于沟道形成区域的部分的绝缘基板的表面上形成岛状导电膜，并且被绝缘膜覆盖以形成突出部。 在沉积非晶半导体膜以覆盖突出部分之后，用激光照射非晶半导体膜以使其熔化并结晶。 突出部分上的熔融半导体的一部分流入与突出部分的两侧相邻的区域，这导致半导体膜在突出部分（沟道形成区域）上的厚度减小。

公开(公告)号：US20130075732A1

公开(公告)日：2013-03-28

申请号：US13604962

申请日：2012-09-06

申请人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

发明人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.

摘要翻译： 提供具有高电特性的小型化晶体管，其产率高。 在包括晶体管的半导体器件中，实现了高性能，高可靠性和高生产率。 在包括晶体管的半导体器件中，依次堆叠其中设置有侧壁绝缘层的侧表面上的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管，源极和漏极电极层被设置为与 氧化物半导体膜和侧壁绝缘层。 在制造半导体器件的过程中，层叠导电膜和层间绝缘膜以覆盖氧化物半导体膜，侧壁绝缘层和栅极电极层，以及栅极上的层间绝缘膜和导电膜 通过化学机械抛光方法去除层，从而形成源极和漏极电极层。

公开(公告)号：US20110287605A1

公开(公告)日：2011-11-24

申请号：US13198171

申请日：2011-08-04

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US20110193080A1

公开(公告)日：2011-08-11

申请号：US13014081

申请日：2011-01-26

申请人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

发明人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  Y10T428/24421

摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.

摘要翻译： 一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。 源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。 侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

公开(公告)号：US20130001571A1

公开(公告)日：2013-01-03

申请号：US13615805

申请日：2012-09-14

申请人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Motomu KURATA ,  Hiroyuki HATA ,  Mitsuhiro ICHIJO ,  Takashi OHTSUKI ,  Aya ANZAI ,  Masayuki SAKAKURA

发明人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Motomu KURATA ,  Hiroyuki HATA ,  Mitsuhiro ICHIJO ,  Takashi OHTSUKI ,  Aya ANZAI ,  Masayuki SAKAKURA

IPC分类号： H01L33/08

CPC分类号： H04N5/655 ,  G06F3/02 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/3244 ,  H01L27/3258 ,  H01L27/3276 ,  H01L33/60 ,  H01L51/0005 ,  H01L51/5246 ,  H01L51/56 ,  H01L2224/4847 ,  H01L2227/323 ,  H01L2251/5323 ,  H04N5/642

摘要： The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

摘要翻译： 本发明提供了一种以高成本低成本制造高度可靠的显示装置的方法。 根据本发明，由绝缘层覆盖由于接触开口而产生的台阶，以减小台阶，并且被加工成平缓的形状。 布线等形成为与绝缘层接触，从而增强布线等的覆盖。 此外，通过用包封材料密封包括显示装置中具有透水性的有机材料的层，可以防止由诸如水等污染物引起的发光元件的劣化。 由于密封材料形成在显示装置的驱动电路区域的一部分中，所以显示装置的边框可以变窄。

公开(公告)号：US20120193625A1

公开(公告)日：2012-08-02

申请号：US13357902

申请日：2012-01-25

申请人： Shinya SASAGAWA ,  Motomu KURATA

发明人： Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/7869

摘要： An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

摘要翻译： 本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。 形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。

公开(公告)号：US20110147745A1

公开(公告)日：2011-06-23

申请号：US12973123

申请日：2010-12-20

申请人： Shinya SASAGAWA ,  Akihiro ISHIZUKA ,  Shinobu FURUKAWA ,  Motomu KURATA

发明人： Shinya SASAGAWA ,  Akihiro ISHIZUKA ,  Shinobu FURUKAWA ,  Motomu KURATA

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： An embodiment is a thin film transistor which includes a gate electrode layer, a gate insulating layer provided so as to cover the gate electrode layer; a first semiconductor layer entirely overlapped with the gate electrode layer; a second semiconductor layer provided over and in contact with the first semiconductor layer and having a lower carrier mobility than the first semiconductor layer; an impurity semiconductor layer provided in contact with the second semiconductor layer; a sidewall insulating layer provided so as to cover at least a sidewall of the first semiconductor layer; and a source and drain electrode layers provided in contact with at least the impurity semiconductor layer. The second semiconductor layer may consist of parts which are apart from each other over the first semiconductor layer.

摘要翻译： 一个实施例是一种薄膜晶体管，其包括栅极电极层，设置为覆盖栅极电极层的栅极绝缘层; 与栅电极层完全重叠的第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触，并具有比第一半导体层低的载流子迁移率; 设置成与所述第二半导体层接触的杂质半导体层; 侧壁绝缘层，设置成覆盖所述第一半导体层的至少一个侧壁; 以及与至少所述杂质半导体层接触地设置的源极和漏极电极层。 第二半导体层可以由在第一半导体层上彼此分开的部分组成。

公开(公告)号：US20090239354A1

公开(公告)日：2009-09-24

申请号：US12399047

申请日：2009-03-06

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US20110147755A1

公开(公告)日：2011-06-23

申请号：US12972994

申请日：2010-12-20

申请人： Hidekazu MIYAIRI ,  Shinya SASAGAWA ,  Motomu KURATA

发明人： Hidekazu MIYAIRI ,  Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L29/786

CPC分类号： H01L29/78678 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78648

摘要： A thin film transistor having favorable electric characteristics with high productively is provided. The thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, an impurity semiconductor layer which is in contact with part of the semiconductor layer and functions as a source region and a drain region, and a wiring in contact with the impurity semiconductor layer. The semiconductor layer includes a microcrystalline semiconductor region having a concave-convex shape, which is formed on the gate insulating layer side, and an amorphous semiconductor region in contact with the microcrystalline semiconductor region. A barrier region is provided between the semiconductor layer and the wiring.

摘要翻译： 提供了具有良好的电特性的高效生产的薄膜晶体管。 薄膜晶体管包括覆盖栅极的栅极绝缘层，与栅极绝缘层接触的半导体层，与半导体层的一部分接触并用作源极区域和漏极区域的杂质半导体层， 以及与杂质半导体层接触的布线。 半导体层包括形成在栅绝缘层侧的具有凹凸形状的微晶半导体区域和与微晶半导体区域接触的非晶半导体区域。 在半导体层和布线之间设置有阻挡区域。