公开(公告)号：US08592908B2

公开(公告)日：2013-11-26

申请号：US13177585

申请日：2011-07-07

申请人： Shunpei Yamazaki ,  Mitsuhiro Ichijo ,  Makoto Furuno ,  Takashi Ohtsuki ,  Kenichi Okazaki ,  Tetsuhiro Tanaka ,  Seiji Yasumoto

发明人： Shunpei Yamazaki ,  Mitsuhiro Ichijo ,  Makoto Furuno ,  Takashi Ohtsuki ,  Kenichi Okazaki ,  Tetsuhiro Tanaka ,  Seiji Yasumoto

IPC分类号： H01L29/06

CPC分类号： H01L21/76254 ,  H01L21/84

摘要： To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.

摘要翻译： 为了提供包括适用于实际使用的结晶半导体层的半导体衬底，以及使用与半导体层的材料不同的材料用于支撑衬底，以及使用该半导体衬底的半导体器件。 半导体基板包括形成接合面的接合层，由含氮的绝缘材料形成的阻挡层，由包含小于20at的氮的绝缘材料形成的凸版层。 ％和氢气在1 at。 ％至20 at。 ％，以及含有卤素的绝缘层，在支撑基板和单晶半导体层之间。 半导体器件至少部分地包括上述结构，并且通过使用SiH 4和N 2 O作为源气体的微波等离子体CVD方法形成的栅极绝缘层与单晶半导体层接触。

公开(公告)号：US08552425B2

公开(公告)日：2013-10-08

申请号：US13157637

申请日：2011-06-10

申请人： Mitsuhiro Ichijo ,  Toshiya Endo ,  Kunihiko Suzuki

发明人： Mitsuhiro Ichijo ,  Toshiya Endo ,  Kunihiko Suzuki

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/477 ,  H01L29/247 ,  H01L29/42384 ,  H01L29/47 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78696

摘要： An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×1020 atoms/cm3 and a fluorine concentration greater than or equal to 1×1020 atoms/cm3 is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.

公开(公告)号：US20120248470A1

公开(公告)日：2012-10-04

申请号：US13486017

申请日：2012-06-01

申请人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Motomu KURATA ,  Hiroyuki HATA ,  Mitsuhiro ICHIJO ,  Takashi OHTSUKI ,  Aya ANZAI ,  Masayuki SAKAKURA

发明人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Motomu KURATA ,  Hiroyuki HATA ,  Mitsuhiro ICHIJO ,  Takashi OHTSUKI ,  Aya ANZAI ,  Masayuki SAKAKURA

IPC分类号： H01L33/08

CPC分类号： H04N5/655 ,  G06F3/02 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/3244 ,  H01L27/3258 ,  H01L27/3276 ,  H01L33/60 ,  H01L51/0005 ,  H01L51/5246 ,  H01L51/56 ,  H01L2224/4847 ,  H01L2227/323 ,  H01L2251/5323 ,  H04N5/642

摘要： The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

摘要翻译： 本发明提供了一种以高成本低成本制造高度可靠的显示装置的方法。 根据本发明，由绝缘层覆盖由于接触开口而产生的台阶，以减小台阶，并且被加工成平缓的形状。 布线等形成为与绝缘层接触，从而增强布线等的覆盖。 此外，通过用包封材料密封包括显示装置中具有透水性的有机材料的层，可以防止由诸如水等污染物引起的发光元件的劣化。 由于密封材料形成在显示装置的驱动电路区域的一部分中，所以显示装置的边框可以变窄。

公开(公告)号：US08247315B2

公开(公告)日：2012-08-21

申请号：US12400844

申请日：2009-03-10

申请人： Makoto Furuno ,  Tetsuo Sugiyama ,  Taichi Nozawa ,  Mitsuhiro Ichijo ,  Ryota Tajima ,  Shunpei Yamazaki

发明人： Makoto Furuno ,  Tetsuo Sugiyama ,  Taichi Nozawa ,  Mitsuhiro Ichijo ,  Ryota Tajima ,  Shunpei Yamazaki

IPC分类号： H01L21/20

CPC分类号： H01L27/127 ,  C23C16/24 ,  C23C16/509 ,  H01L21/67207 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.

摘要翻译： 通过包括串联连接的第一和第二涡轮分子泵的抽空单元，将反应室中的极限压力降低到超高真空。 通过刀刃式金属密封法兰，反应室中的泄漏量减少。 将微晶半导体膜和非晶半导体膜堆叠在相同的反应室中，其中压力降低至超高真空。 通过形成覆盖微晶半导体膜的表面的非晶半导体膜，可以防止微晶半导体膜的氧化。

公开(公告)号：US20120156556A1

公开(公告)日：2012-06-21

申请号：US13307052

申请日：2011-11-30

申请人： Kazutaka KURIKI ,  Mitsuhiro Ichijo ,  Toshiya Endo

发明人： Kazutaka KURIKI ,  Mitsuhiro Ichijo ,  Toshiya Endo

IPC分类号： H01M10/02 ,  H01M4/66 ,  H01M4/58

CPC分类号： H01M4/366 ,  H01M4/0428 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/386 ,  H01M4/48 ,  H01M4/661 ,  Y02E60/122 ,  Y02P70/54

摘要： An electrode in which a silicon layer is provided over a current collector, a thin film layer having a thickness within a certain range is provided on a surface of the silicon layer, and the thin film layer contains fluorine, is used for a power storage device. The thickness of the thin film layer containing fluorine is greater than 0 nm and less than or equal to 10 nm, preferably greater than or equal to 4 nm and less than or equal to 9 nm. The fluorine concentration of the thin film layer containing fluorine is preferably as high as possible, and the nitrogen concentration, the oxygen concentration, and the hydrogen concentration thereof are preferably as low as possible.

摘要翻译： 在硅层的表面上设置有在集电体上设置硅层的电极，厚度在一定范围内的薄膜层，薄膜层含有氟，用于蓄电装置 。 含氟的薄膜层的厚度大于0nm且小于或等于10nm，优选大于或等于4nm且小于或等于9nm。 含氟的薄膜层的氟浓度优选尽可能高，氮浓度，氧浓度和氢浓度优选尽可能低。

公开(公告)号：US20110315969A1

公开(公告)日：2011-12-29

申请号：US13225586

申请日：2011-09-06

申请人： Satoshi MURAKAMI ,  Mitsuhiro ICHIJO ,  Taketomi ASAMI

发明人： Satoshi MURAKAMI ,  Mitsuhiro ICHIJO ,  Taketomi ASAMI

IPC分类号： H01L27/32

CPC分类号： H01L27/3258 ,  H01L21/7684 ,  H01L21/76841 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3248 ,  H01L33/0041 ,  H01L51/5221 ,  H01L51/5253 ,  H01L2227/323 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.

摘要翻译： 在使用阴极中含有碱土类金属的材料的情况下，担心从EL元件向所产生的TFT扩散杂质离子（如碱土类金属离子）扩散至产生的TFT TFT的特性变化。 因此，作为设置在TFT和EL元件之间的绝缘膜，含有不仅阻挡诸如碱土金属离子等杂质离子扩散的材料的膜，而且还积极地吸收杂质离子如碱土金属 离子。

公开(公告)号：US20110284959A1

公开(公告)日：2011-11-24

申请号：US13099613

申请日：2011-05-03

申请人： Kunio KIMURA ,  Mitsuhiro ICHIJO ,  Toshiya ENDO

发明人： Kunio KIMURA ,  Mitsuhiro ICHIJO ,  Toshiya ENDO

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/78606 ,  G02F1/133345 ,  G02F1/13394 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2203/64 ,  H01L21/3003 ,  H01L21/31629 ,  H01L27/1225 ,  H01L27/14616 ,  H01L27/3262 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： One object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. Another object is to manufacture a highly reliable semiconductor device in a high yield. In a top-gate staggered transistor including an oxide semiconductor film, as a first gate insulating film in contact with the oxide semiconductor film, a silicon oxide film is formed by a plasma CVD method with use of a deposition gas containing silicon fluoride and oxygen; and as a second gate insulating film stacked over the first gate insulating film, a silicon oxide film is formed by a plasma CVD method with use of a deposition gas containing silicon hydride and oxygen.

摘要翻译： 一个目的是提供一种具有稳定的电特性和高可靠性的氧化物半导体的半导体装置。 另一个目的是以高产量制造高度可靠的半导体器件。 在包括氧化物半导体膜的顶栅交错晶体管中，作为与氧化物半导体膜接触的第一栅极绝缘膜，通过使用含有氟化硅和氧的沉积气体的等离子体CVD法形成氧化硅膜; 并且作为层叠在第一栅极绝缘膜上的第二栅极绝缘膜，通过使用含有氢化硅和氧的沉积气体的等离子体CVD法形成氧化硅膜。

公开(公告)号：US07989273B2

公开(公告)日：2011-08-02

申请号：US12155052

申请日：2008-05-29

申请人： Shunpei Yamazaki ,  Mitsuhiro Ichijo ,  Makoto Furuno ,  Takashi Ohtsuki ,  Kenichi Okazaki ,  Tetsuhiro Tanaka ,  Seiji Yasumoto

发明人： Shunpei Yamazaki ,  Mitsuhiro Ichijo ,  Makoto Furuno ,  Takashi Ohtsuki ,  Kenichi Okazaki ,  Tetsuhiro Tanaka ,  Seiji Yasumoto

IPC分类号： H01L21/336

CPC分类号： H01L21/76254 ,  H01L21/84

摘要： To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.

摘要翻译： 为了提供包括适用于实际使用的结晶半导体层的半导体衬底，以及使用与半导体层的材料不同的材料用于支撑衬底，以及使用该半导体衬底的半导体器件。 半导体基板包括形成接合面的接合层，由含氮的绝缘材料形成的阻挡层，由包含小于20at的氮的绝缘材料形成的凸版层。 ％和氢气在1 at。 ％至20 at。 ％，以及含有卤素的绝缘层，在支撑基板和单晶半导体层之间。 半导体器件至少部分地包括上述结构，并且通过使用SiH 4和N 2 O作为源气体的微波等离子体CVD方法形成的栅极绝缘层与单晶半导体层接触。

公开(公告)号：US20110111557A1

公开(公告)日：2011-05-12

申请号：US12938527

申请日：2010-11-03

申请人： Mitsuhiro ICHIJO ,  Tetsuhiro TANAKA ,  Seiji YASUMOTO ,  Shun MASHIRO ,  Yoshiaki OIKAWA ,  Kenichi OKAZAKI

发明人： Mitsuhiro ICHIJO ,  Tetsuhiro TANAKA ,  Seiji YASUMOTO ,  Shun MASHIRO ,  Yoshiaki OIKAWA ,  Kenichi OKAZAKI

IPC分类号： H01L21/44

CPC分类号： H01L21/44 ,  C23C16/308 ,  C23C16/45578 ,  C23C16/511 ,  H01J37/32192 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/34 ,  H01L21/02274 ,  H01L21/0237 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/02631 ,  H01L21/67167 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma. Accordingly, dangling bonds in the gate insulating film are reduced and the quality of the interface between the gate insulating film and the oxide semiconductor is improved.

摘要翻译： 本发明的目的是高速驱动半导体器件或提高半导体器件的可靠性。 在半导体器件的制造方法中，其中在绝缘性的衬底上形成栅电极，在栅电极上形成栅极绝缘膜，并且在栅极绝缘膜上形成氧化物半导体膜，栅极 通过使用高密度等离子体的沉积处理形成绝缘膜。 因此，栅极绝缘膜中的悬挂键减少，并且栅极绝缘膜和氧化物半导体之间的界面的质量得到改善。

公开(公告)号：US07538011B2

公开(公告)日：2009-05-26

申请号：US11882907

申请日：2007-08-07

申请人： Shunpei Yamazaki ,  Osama Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

发明人： Shunpei Yamazaki ,  Osama Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

IPC分类号： H01L21/322

CPC分类号： H01L29/66757 ,  G02F1/13454 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678

摘要： An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing a noble (rare) gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.

摘要翻译： 目的是减少高温（等于或高于600℃）的热处理工艺步骤，达到较低的温度（等于或小于600℃）的工艺，并简化工艺步骤并增加 在制造半导体器件的方法中的吞吐量。 通过本发明，在具有结晶结构的第一半导体膜上形成有阻挡层，第二半导体膜和含有贵重（稀有）气体元素的第三半导体膜。 进行吸气，并且包含在第一半导体膜中的金属元素通过热处理工艺通过阻挡层和第二半导体膜，并移动到第三半导体膜。 然后去除第二半导体膜和第三半导体膜，其中阻挡层用作蚀刻停止层。