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公开(公告)号：US4404029A
公开(公告)日：1983-09-13
申请号：US350379
申请日：1982-02-19
CPC分类号： C04B35/4682
摘要： A D-E hysteresis loop of ferroelectrics known in the art has a square shape when the ferroelectrics are a BaTiO.sub.3 single crystal. Such ferroelectrics are used as a non-linear dielectric element of, for example a pulse generating device. The non-linear dielectric element according to the present invention consists of a polycrystal mainly composed of Ba(Ti.sub.0.90-0.98 Sn.sub.0.02-1.00)O.sub.3 and having an average grain diameter of from 10 to 60 .mu.m. The non-linearity is excellent and the temperature dependence of the non-linearity is considerably low.
摘要翻译： 当铁电体是BaTiO 3单晶时，本领域已知的铁电体的D-E磁滞回线具有正方形形状。 这种铁电体用作例如脉冲发生装置的非线性介电元件。 根据本发明的非线性电介质元件由主要由Ba（Ti0.90-0.98Sn0.02-1.00）O3组成的平均粒径为10至60μm的多晶体组成。 非线性非常好，非线性的温度依赖性相当低。
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公开(公告)号：US4447549A
公开(公告)日：1984-05-08
申请号：US476250
申请日：1983-03-22
申请人： Sho Masujima , Masahide Shibuya , Iwaya Shoichi , Kenichi Umeda , Yasunobu Oikawa , Hisao Abe , Yoshifumi Midori , Shinobu Fujiwara , Nobuaki Kikuchi
发明人： Sho Masujima , Masahide Shibuya , Iwaya Shoichi , Kenichi Umeda , Yasunobu Oikawa , Hisao Abe , Yoshifumi Midori , Shinobu Fujiwara , Nobuaki Kikuchi
CPC分类号： H01B3/12 , C04B35/4682 , H05B41/046
摘要： A D-E hysteresis loop of ferroelectrics known in the art has a square shape when the ferroelectrics are a BaTiO.sub.3 single crystal. Such ferroelectrics are used as a non-linear dielectric element of, for example a pulse generating device. The non-linear dielectric element according to the present invention consists of a polycrystal, which is mainly composed of BaTiO.sub.3 and has the chemical composition expressed by the formula A.sub.y B.sub.z O.sub.3, wherein the molar ratio of y/z ranges from 0.92 to 0.99. The non-linearity is excellent and the temperature dependence of the A.sub.y B.sub.z O.sub.3 composition is considerably low.
摘要翻译： 当铁电体是BaTiO 3单晶时，本领域已知的铁电体的D-E磁滞回线具有正方形形状。 这种铁电体用作例如脉冲发生装置的非线性介电元件。 根据本发明的非线性介电元件由主要由BaTiO 3组成并具有由式AyBzO3表示的化学组成的多晶体组成，其中y / z的摩尔比范围为0.92至0.99。 非线性优异，并且AyBzO3组合物的温度依赖性相当低。
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公开(公告)号：US08411411B2
公开(公告)日：2013-04-02
申请号：US12876611
申请日：2010-09-07
申请人： Yasunobu Oikawa , Yoshihiko Yano
发明人： Yasunobu Oikawa , Yoshihiko Yano
摘要： To provide a thin-film capacitor capable of preventing the degradation of electrical characteristics caused by direct contact between an adhesion layer of a terminal electrode and a dielectric layer, to increase the reliability. The thin-film capacitor comprises: a dielectric layer deposited on a base electrode; an upper electrode layer deposited on the dielectric layer; a terminal electrode including an adhesion layer, a seed layer, and a plating layer; a resin layer for wiring provided between the upper electrode layer and the terminal electrode for isolating the upper electrode layer from the terminal electrode; and a wiring layer provided so as to extend through the resin layer for wiring in contact with the adhesion layer for electrically connecting the upper electrode layer and the terminal electrode, wherein a composition of the wiring layer differs from that of the adhesion layer of the terminal electrode, and wherein a reducing power of the wiring layer to the dielectric layer is smaller than that of the adhesion layer.
摘要翻译： 提供能够防止由端子电极和电介质层的粘附层之间的直接接触引起的电特性劣化的薄膜电容器，以提高可靠性。 薄膜电容器包括：沉积在基极上的电介质层; 沉积在电介质层上的上电极层; 包括粘合层，种子层和镀层的端子电极; 用于在上电极层和端子电极之间设置用于将上电极层与端子电极隔离的布线用树脂层; 以及布线层，其设置成延伸穿过用于电连接上电极层和端子电极的粘合层接触的布线用树脂层，其中布线层的组成与端子的粘合层的组成不同 电极，并且其中所述布线层到所述电介质层的还原能力小于所述粘合层的还原能力。
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4.发明授权Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and saw device 有权包装基板及其制造方法，集成电路装置及其制造方法以及锯装置公开(公告)号：US07015556B2
公开(公告)日：2006-03-21
申请号：US10813393
申请日：2004-03-31
申请人： Masahiro Nakano , Katsuhiko Gunji , Yasunobu Oikawa , Katsuo Sato
发明人： Masahiro Nakano , Katsuhiko Gunji , Yasunobu Oikawa , Katsuo Sato
CPC分类号： H03H9/1071 , H01L2224/16225 , H01L2224/45144 , H03H9/0585 , H03H9/059 , H03H9/08 , H01L2924/00
摘要： A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23 are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 μmRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.
摘要翻译： 衬底电极12a的基本部分层21，其在陶瓷的衬底构件上电连接到突出电极13。 对其上形成有碱性部分层21的基材进行烧结。 研磨烧结基板部件中的基体部分层21的表面。 在抛光的基底层21上形成镀层22,23，使得基板电极12a的表面粗糙度例如可以不大于0.1μmumRMS。 因此，可以提高通过倒装芯片方法安装在封装基板上的集成电路元件的结合强度。
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公开(公告)号：US08605410B2
公开(公告)日：2013-12-10
申请号：US12876648
申请日：2010-09-07
申请人： Yasunobu Oikawa , Yoshihiko Yano
发明人： Yasunobu Oikawa , Yoshihiko Yano
摘要： To provide a thin-film capacitor capable of improving the stability of electric connection between an internal electrode layer and a connection electrode. The thin-film capacitor comprises: two or more dielectric layers deposited above a base electrode; an internal electrode layer being deposited between the dielectric layers and having a projecting portion which projects from the dielectric layer when seen from a laminating direction; and a connection electrode electrically connected to the internal electrode layer via at least a part of a surface and an end face of the internal electrode layer included in the projecting portion, wherein a ratio L/t between a projection amount L of the projecting portion of the internal electrode layer with respect to the dielectric layer and a thickness t of the internal electrode layer is 0.5 to 120.
摘要翻译： 提供能够提高内部电极层和连接电极之间的电连接的稳定性的薄膜电容器。 薄膜电容器包括：沉积在基极上方的两个或多个介电层; 在电介质层之间沉积内部电极层，当从层叠方向观察时，具有从电介质层突出的突出部分; 以及连接电极，其经由包括在所述突出部中的所述内部电极层的表面和端面的至少一部分与所述内部电极层电连接，其中，所述突起部的突出部L的突出量L 内部电极层相对于电介质层和内部电极层的厚度t为0.5〜120。
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公开(公告)号：US08498095B2
公开(公告)日：2013-07-30
申请号：US12956060
申请日：2010-11-30
申请人： Yoshihiko Yano , Yasunobu Oikawa , Kenji Horino , Hitoshi Saita
发明人： Yoshihiko Yano , Yasunobu Oikawa , Kenji Horino , Hitoshi Saita
摘要： A thin-film capacitor that is less prone to generation of internal cracking or peeling is provided. In a thin-film capacitor according to the present embodiment, because through holes H are formed in internal electrodes containing Ni as a principal component in a lamination direction, a surface area of at least some of the through holes H is in the range of 0.19 μm2 to 7.0 μm2, and a ratio of a surface area of the through holes H to a surface area of an entire main surface of the internal electrodes is in the range of 0.05% to 5%, peeling or cracking is suppressed from occurring at the boundaries between the internal electrodes and dielectric layers, and as a result, the yield is enhanced.
摘要翻译： 提供了不容易产生内部开裂或剥离的薄膜电容器。 在本实施方式的薄膜电容器中，由于在层叠方向上以Ni为主要成分的内部电极形成贯通孔H，所以贯通孔H的至少一部分的表面积为0.19 m 2〜7.0mum 2，通孔H的表面积与内部电极整个表面的表面积的比例在0.05〜5％的范围内，可以抑制剥离或开裂 内部电极和电介质层之间的边界，结果提高了产率。
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公开(公告)号：US08339766B2
公开(公告)日：2012-12-25
申请号：US12731398
申请日：2010-03-25
申请人： Yoshihiko Yano , Yasunobu Oikawa
发明人： Yoshihiko Yano , Yasunobu Oikawa
IPC分类号： H01G4/228
CPC分类号： H01G4/0085 , H01G4/228 , H01G4/30 , H01G4/33 , H01G9/0029 , H01L28/40
摘要： A method of manufacturing a thin film capacitor, having: a base electrode; dielectric layers consecutively deposited on the base electrode; an internal electrode deposited between the dielectric layers; an upper electrode deposited opposite the base electrode with the dielectric layers and the internal electrode being interposed therebetween; and a cover layer deposited on the upper electrode, has depositing an upper electrode layer which is to be the upper electrode, and a cover film which is to be the cover layer on the unsintered dielectric film which is to be the dielectric layer, to fabricate a lamination component, and sintering the lamination component.
摘要翻译： 一种制造薄膜电容器的方法，其具有：基极; 电介质层连续沉积在基极上; 沉积在介电层之间的内部电极; 与基底电极相对地沉积有电介质层和内部电极之间的上部电极; 和沉积在上电极上的覆盖层，具有沉积作为上电极的上电极层和作为要作为电介质层的未烧结电介质膜上的覆盖层的覆盖膜，以制造 层压部件，并烧结层压部件。
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公开(公告)号：US08294036B2
公开(公告)日：2012-10-23
申请号：US12410699
申请日：2009-03-25
申请人： Shinichiro Kakei , Kenji Horino , Hitoshi Saita , Yasunobu Oikawa
发明人： Shinichiro Kakei , Kenji Horino , Hitoshi Saita , Yasunobu Oikawa
CPC分类号： H05K1/162 , H05K3/382 , H05K2201/0175 , H05K2201/0187 , H05K2201/0355 , H05K2201/09509 , H05K2201/09718 , H05K2201/09763 , H05K2203/033
摘要： In a dielectric element, the side faces are roughened so that the surface roughness Ra is 15 nm or greater. By this means, the area of contact between a glass epoxy resin substrate and insulating material is increased, adhesion with resin substrates is improved, and strength and reliability can be enhanced when buried between two resin substrates. In the dielectric element, the surface roughness Ra of side surfaces is 5000 nm or less, so that when burying the dielectric element between a glass epoxy resin substrate and insulating material, the occurrence of air bubbles between the surface of the dielectric element and the resin can be prevented.
摘要翻译： 在电介质元件中，侧面粗糙化，使得表面粗糙度Ra为15nm以上。 通过这种方式，玻璃环氧树脂基板和绝缘材料之间的接触面积增加，与树脂基板的粘合性提高，并且当埋在两个树脂基板之间时可以提高强度和可靠性。 在电介质元件中，侧面的表面粗糙度Ra为5000nm以下，因此当在玻璃环氧树脂基板和绝缘材料之间埋入电介质元件时，介电元件表面与树脂之间产生气泡 可以防止。
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公开(公告)号：US08149584B2
公开(公告)日：2012-04-03
申请号：US12410685
申请日：2009-03-25
申请人： Hitoshi Saita , Kenji Horino , Yasunobu Oikawa , Shinichiro Kakei
发明人： Hitoshi Saita , Kenji Horino , Yasunobu Oikawa , Shinichiro Kakei
IPC分类号： H05K1/18
CPC分类号： H05K1/162 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/098
摘要： In a dielectric element, the angle θ made by either the top face or the bottom face and the side faces is either 0°
摘要翻译： 在电介质元件中，角度和角度; 由顶面或底面和侧面制成的角度为0°<θ; <89°，或91°<θ; <180°，并且为89°＆lt; l1E以外的角度;＆Thetas;＆nlE; 91°。 通过这种方式，介电元件的侧面与玻璃环氧树脂基板和绝缘材料的接触面积增加，与树脂基板的粘附性提高，并且当埋在两个树脂之间时，可以提高强度和可靠性 底物。
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10.发明授权Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and SAW device 有权包装基板及其制造方法，集成电路装置及其制造方法以及SAW器件公开(公告)号：US07132310B2
公开(公告)日：2006-11-07
申请号：US11333316
申请日：2006-01-18
申请人： Masahiro Nakano , Katsuhiko Gunji , Yasunobu Oikawa , Katsuo Sato
发明人： Masahiro Nakano , Katsuhiko Gunji , Yasunobu Oikawa , Katsuo Sato
CPC分类号： H03H9/1071 , H01L2224/16225 , H01L2224/45144 , H03H9/0585 , H03H9/059 , H03H9/08 , H01L2924/00
摘要： A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 μmRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.
摘要翻译： 衬底电极12a的基本部分层21，其在陶瓷的衬底构件上电连接到突出电极13。 对其上形成有碱性部分层21的基材进行烧结。 研磨烧结基板部件中的基体部分层21的表面。 在抛光的基底层21上形成镀层22,23，使得基板电极12a的表面粗糙度例如可以不大于0.1μmumRMS。 因此，可以提高通过倒装芯片方法安装在封装基板上的集成电路元件的结合强度。
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