公开(公告)号：US06939796B2

公开(公告)日：2005-09-06

申请号：US10390117

申请日：2003-03-14

申请人： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

发明人： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

IPC分类号： B44C1/22 ,  H01L20060101 ,  H01L21/302 ,  H01L21/304 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768 ,  H01L33/00

CPC分类号： H01L21/7684 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136

摘要： A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

摘要翻译： 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 覆盖层部分具有局部不均匀性。 去除覆盖层部分的大部分以平坦化上覆层部分。 映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。 基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

公开(公告)号：US06821899B2

公开(公告)日：2004-11-23

申请号：US10390520

申请日：2003-03-14

申请人： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

发明人： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

IPC分类号： H01L21311

CPC分类号： H01L21/32135 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/7684

摘要： A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

摘要翻译： 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 覆盖层部分包括局部不均匀性。 在覆盖层部分上形成附加层。 附加层和覆盖层部分被平坦化。 平坦化工艺基本上完全除去附加层。

公开(公告)号：US07959984B2

公开(公告)日：2011-06-14

申请号：US11022982

申请日：2004-12-22

申请人： Shrikant P. Lohokare ,  Andrew D. Bailey, III

发明人： Shrikant P. Lohokare ,  Andrew D. Bailey, III

IPC分类号： H05H1/24

CPC分类号： H01J37/32633 ,  C23C16/4404 ,  H01J37/32623

摘要： In a plasma processing system, a method of reducing byproduct deposits on a set of plasma chamber surfaces of a plasma processing chamber is disclosed. The method includes providing a deposition barrier in the plasma processing chamber, the deposition barrier is configured to be disposed in a plasma generating region of the plasma processing chamber, thereby permitting at least some process byproducts produced when a plasma is struck within the plasma processing chamber to adhere to the deposition barrier and reducing the byproduct deposits on the set of plasma processing chamber surfaces.

摘要翻译： 在等离子体处理系统中，公开了一种在等离子体处理室的一组等离子体室表面上减少副产物沉积的方法。 所述方法包括在所述等离子体处理室中设置沉积阻挡层，所述沉积阻挡层被配置为设置在所述等离子体处理室的等离子体产生区域中，从而允许在所述等离子体处理室内等离子体被击中时产生的至少一些过程副产物 以附着到沉积屏障上并减少等离子体处理室表面组上的副产物沉积物。

公开(公告)号：US07413673B2

公开(公告)日：2008-08-19

申请号：US11109921

申请日：2005-04-19

申请人： Shrikant P. Lohokare ,  Andras Kuthi ,  Andrew D. Bailey, III

发明人： Shrikant P. Lohokare ,  Andras Kuthi ,  Andrew D. Bailey, III

IPC分类号： H03J3/12

CPC分类号： H01J37/321 ,  H01J37/32174 ,  H01J37/32431 ,  H01J37/32623

摘要： An apparatus and method for adjusting the voltage applied to a Faraday shield of an inductively coupled plasma etching apparatus is provided. An appropriate voltage is easily and variably applied to a Faraday shield such that sputtering of a plasma can be controlled to prevent and mitigate deposition of non-volatile reaction products that adversely affect an etching process. The appropriate voltage for a particular etching process or step is applied to the Faraday shield by simply adjusting a tuning capacitor. It is not necessary to mechanically reconfigure the etching apparatus to adjust the Faraday shield voltage.

摘要翻译： 提供了一种用于调整施加到电感耦合等离子体蚀刻装置的法拉第屏蔽的电压的装置和方法。 适当的电压容易且可变地施加到法拉第屏蔽，使得可以控制等离子体的溅射以防止和减轻不利地影响蚀刻工艺的非挥发性反应产物的沉积。 通过简单地调整调谐电容器，将特定蚀刻工艺或步骤的适当电压施加到法拉第屏蔽。 不需要机械地重新配置蚀刻装置来调节法拉第屏蔽电压。

公开(公告)号：US07232766B2

公开(公告)日：2007-06-19

申请号：US10769408

申请日：2004-01-30

申请人： Andrew D. Bailey, III ,  Shrikant P. Lohokare

发明人： Andrew D. Bailey, III ,  Shrikant P. Lohokare

IPC分类号： H01L21/302

CPC分类号： H01L21/32115 ,  C23G5/00 ,  H01J37/32522 ,  H01J2237/022 ,  H01L21/32136 ,  H01L21/67034 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/76838 ,  H01L21/7684

摘要： A system and method of passivating an exposed conductive material includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber. A hydrogen species plasma is formed in the process chamber. A surface layer species is reduced from a top surface of the substrate is reduced. The reduced surface layer species are purged from the process chamber.

摘要翻译： 钝化暴露的导电材料的系统和方法包括将衬底放置在处理室中并将氢物质注入到处理室中。 在处理室中形成氢物质等离子体。 从基板的顶面减少的表面层物质减少。 还原的表面层物质从处理室中清除。

公开(公告)号：US07217649B2

公开(公告)日：2007-05-15

申请号：US10769522

申请日：2004-01-30

申请人： Andrew D. Bailey, III ,  Shrikant P. Lohokare

发明人： Andrew D. Bailey, III ,  Shrikant P. Lohokare

IPC分类号： H01L21/4763

CPC分类号： H01L21/67051 ,  H01J37/32522 ,  H01J2237/022 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/67034 ,  H01L21/6708 ,  H01L21/76819 ,  H01L21/7684

摘要： A system and method for forming a semiconductor in a dual damascene structure including receiving a patterned semiconductor substrate. The semiconductor substrate having a first conductive interconnect material filling multiple features in the pattern. The first conductive interconnect material having an overburden portion. The over burden portion is planarized. The over burden portion is substantially entirely removed in the planarizing process. A mask layer is reduced and a subsequent dielectric layer is formed on the planarized over burden portion. A mask is formed on the subsequent dielectric layer. One or more features are formed in the subsequent dielectric layer and the features are filled with a second conductive interconnect material.

摘要翻译： 一种用于在双镶嵌结构中形成半导体的系统和方法，包括接收图案化的半导体衬底。 半导体衬底具有填充图案中的多个特征的第一导电互连材料。 第一导电互连材料具有覆盖层部分。 过度负载部分被平坦化。 在平坦化处理中基本上完全去除过度负担部分。 掩模层被还原，并且在平坦化的过度部分上形成随后的介电层。 在随后的介电层上形成掩模。 在随后的介电层中形成一个或多个特征，并且特征填充有第二导电互连材料。

公开(公告)号：US07140374B2

公开(公告)日：2006-11-28

申请号：US10802460

申请日：2004-03-16

申请人： Andrew D. Bailey, III ,  Shrikant P. Lohokare ,  Arthur M. Howald ,  Yunsang Kim

发明人： Andrew D. Bailey, III ,  Shrikant P. Lohokare ,  Arthur M. Howald ,  Yunsang Kim

IPC分类号： B08B9/00 ,  B44C1/22

CPC分类号： B08B7/00 ,  B08B7/0035 ,  B08B7/0071 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32862 ,  H01J2237/022 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/67034 ,  H01L21/67051 ,  H01L21/67069 ,  H01L21/6708 ,  H01L21/7684 ,  Y10S438/905

摘要： A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.

公开(公告)号：US07129167B1

公开(公告)日：2006-10-31

申请号：US10879598

申请日：2004-06-28

申请人： Andrew D. Bailey, III ,  Shrikant P. Lohokare ,  Yunsang Kim ,  Simon McClatchie

发明人： Andrew D. Bailey, III ,  Shrikant P. Lohokare ,  Yunsang Kim ,  Simon McClatchie

IPC分类号： H01L21/44

CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/67046 ,  H01L21/67051

摘要： A method of cleaning a substrate includes receiving a substrate and applying a stress-free cleaning process to the top surface of the substrate. The substrate includes a top surface that is substantially free of device dependent planarity nonuniformities and device independent planarity nonuniformities. The top surface also includes a first material and a device structure formed in the first material, the device structure being formed from a second material. The device structure has a device surface exposed. The device surface has a first surface roughness. A system for stress-free cleaning a substrate is also described.

摘要翻译： 清洁基板的方法包括接收基板并向基板的顶表面施加无应力清洁处理。 衬底包括基本上没有与器件相关的平面不均匀性和器件独立平面度不均匀性的顶表面。 顶表面还包括形成在第一材料中的第一材料和器件结构，该器件结构由第二材料形成。 器件结构具有暴露的器件表面。 器件表面具有第一表面粗糙度。 还描述了一种用于无应力清洁基底的系统。

公开(公告)号：US08211238B2

公开(公告)日：2012-07-03

申请号：US11444942

申请日：2006-05-31

申请人： Andrew D. Bailey, III ,  Shrikant P. Lohokare ,  Arthur M. Howald ,  Yunsang Kim

发明人： Andrew D. Bailey, III ,  Shrikant P. Lohokare ,  Arthur M. Howald ,  Yunsang Kim

IPC分类号： C25F3/12 ,  B08B9/027

CPC分类号： B08B7/00 ,  B08B7/0035 ,  B08B7/0071 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32862 ,  H01J2237/022 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/67034 ,  H01L21/67051 ,  H01L21/67069 ,  H01L21/6708 ,  H01L21/7684 ,  Y10S438/905

摘要： A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.

摘要翻译： 一种用于清洁处理室的方法，包括将处理室的内表面加热至第一温度。 第一个温度足以使第一个物质变得挥发。 第一种可以是沉积在内表面上的几种物质之一。 将清洁化学品注入到处理室中。 清洁化学品可以与第二种物质反应以将第二种类转化为第一种。 挥发的第一种也可以从处理室输出。 还描述了用于清洁处理室的系统。

公开(公告)号：US08017516B2

公开(公告)日：2011-09-13

申请号：US11732608

申请日：2007-04-03

申请人： Andrew D. Bailey, III ,  Shrikant P. Lohokare

发明人： Andrew D. Bailey, III ,  Shrikant P. Lohokare

IPC分类号： H01L21/4763

CPC分类号： H01L21/67051 ,  H01J37/32522 ,  H01J2237/022 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/67034 ,  H01L21/6708 ,  H01L21/76819 ,  H01L21/7684

摘要： A system and method for forming a planar dielectric layer includes identifying a non-planarity in the dielectric layer, forming one or more additional dielectric layers over the dielectric layer and planarizing at least one of the additional dielectric layers wherein the one or more additional dielectric layers include at least one of a spin-on-glass layer and at least one of a low-k dielectric material layer and wherein each one of the one or more additional dielectric layers having a thickness of less than about 1000 angstroms and wherein the one or more additional dielectric layers has a total thickness of between about 1000 and about 4000 angstroms.

摘要翻译： 用于形成平面电介质层的系统和方法包括识别电介质层中的非平面性，在电介质层上形成一个或多个附加的电介质层，并平坦化至少一个附加电介质层，其中一个或多个附加电介质层 包括旋涂玻璃层和低k介电材料层中的至少一个中的至少一个，并且其中所述一个或多个附加电介质层中的每一个具有小于约1000埃的厚度，并且其中所述一个或多个 更多的附加电介质层的总厚度在约1000和约4000埃之间。