公开(公告)号：US06897523B2

公开(公告)日：2005-05-24

申请号：US10211705

申请日：2002-08-05

申请人： Shuichi Ueno ,  Haruo Furuta ,  Shigehiro Kuge ,  Hiroshi Kato

发明人： Shuichi Ueno ,  Haruo Furuta ,  Shigehiro Kuge ,  Hiroshi Kato

IPC分类号： H01L29/78 ,  H01L29/792 ,  H01L29/861 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L29/8616

摘要： A semiconductor device is provided which includes a diode formed of a MISFET and having a current-voltage characteristic close to that of an ideal diode. Negatively charged particles (e.g. electrons: 8a) are trapped on the drain region (2) side of a silicon nitride film (4b) sandwiched between films of silicon oxide (4a, 4c). When a bias voltage is applied between the drain and source with the negatively charged particles (8a) thus trapped and in-channel charged particles (9a) induced by them, the MISFET exhibits different threshold values for channel formation depending on whether it is a forward bias or a reverse bias. That is to say, when a reverse bias is applied, the channel forms insufficiently and the source-drain current is less likely to flow, while the channel forms sufficiently and a large source-drain current flows when a forward bias is applied. This offers a current-voltage characteristic close to that of the ideal diode.

摘要翻译： 提供一种半导体器件，其包括由MISFET形成的二极管，其具有接近于理想二极管的电流 - 电压特性。 负电粒子（例如电子：8a）被捕获在夹在氧化硅（4a，4c）的膜之间的氮化硅膜（4b）的漏极区（2）侧上。 当在漏极和源极之间施加偏置电压时，带负电荷的颗粒（8a）被这样捕获并且由它们引起的通道内带电粒子（9a），MISFET对通道形成具有不同的阈值，取决于它是否是 正向偏压或反向偏压。 也就是说，当施加反向偏压时，沟道形成不充分，并且源极 - 漏极电流不太可能流动，而沟道形成充分，并且当施加正向偏压时流过大的源极 - 漏极电流。 这提供了接近理想二极管的电流电压特性。

公开(公告)号：US07157773B2

公开(公告)日：2007-01-02

申请号：US10330093

申请日：2002-12-30

申请人： Hiroshi Kato ,  Shigehiro Kuge ,  Hideyuki Noda ,  Fukashi Morishita ,  Shuichi Ueno

发明人： Hiroshi Kato ,  Shigehiro Kuge ,  Hideyuki Noda ,  Fukashi Morishita ,  Shuichi Ueno

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L21/28282 ,  H01L29/792

摘要： A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.

摘要翻译： 非易失性半导体存储器件的存储单元通过ONO膜形成在硅衬底上形成的硅层上。 存储单元具有在硅层中形成的源区和漏区，ONO膜和栅电极。 ONO膜和ONO膜包括具有捕获电荷的电荷陷阱部分的氮化物膜。

公开(公告)号：US06731535B1

公开(公告)日：2004-05-04

申请号：US10455523

申请日：2003-06-06

申请人： Tsukasa Ooishi ,  Shuichi Ueno ,  Shigehiro Kuge

发明人： Tsukasa Ooishi ,  Shuichi Ueno ,  Shigehiro Kuge

IPC分类号： G11C1114

CPC分类号： H01L27/224 ,  G11C11/16 ,  H01L27/228

摘要： A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.

摘要翻译： 非易失性半导体存储器件包括硅衬底，位线，字线和存储单元。 位线位于硅衬底的主表面上方，并且字线被提供以与位线相交。 存储单元位于位线和字线相交的区域，并且其一端电连接到位线，另一端电连接到字线。 存储单元包括串联电连接的TMR元件和存取二极管。 存取二极管包括n型硅层和通过熔融重结晶重结晶的p型硅层，并且在n型硅层和p型硅层之间的界面处具有pn结。 结果，可以廉价地制造尺寸减小并且具有高性能的非易失性半导体存储器件。

公开(公告)号：US08546151B2

公开(公告)日：2013-10-01

申请号：US12528854

申请日：2008-02-25

申请人： Haruo Furuta ,  Shuichi Ueno ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Takeharu Kuroiwa ,  Lien-Chang Wang ,  Eugene Chen ,  Yiming Huai

发明人： Haruo Furuta ,  Shuichi Ueno ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Takeharu Kuroiwa ,  Lien-Chang Wang ,  Eugene Chen ,  Yiming Huai

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  B82Y10/00 ,  H01L27/228

摘要： Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode. Also disclosed is a magnetic storage device comprising an interlayer insulating film provided with a wiring layer, an insulating film formed on the interlayer insulating film, an opening formed in the insulating film so that the wiring layer is exposed therefrom, a barrier metal layer provided so as to cover the inner surface of the opening, a lower electrode formed on the barrier metal so as to fill the opening, and a TMR element formed on the lower electrode.

摘要翻译： 公开了一种制造包括TMR元件的磁存储装置的方法，该方法包括在具有布线层的层间绝缘膜上形成绝缘膜的步骤，用于在绝缘膜上形成开口的开口形成步骤， 布线层暴露于其中，金属层形成步骤用于在绝缘层上形成金属层以使其开口被填充; CMP步骤，用于通过CMP方法在绝缘层上抛光和去除金属层，并形成金属 剩余在开口中的层形成下电极，以及在下电极上形成TMR元件的步骤。 还公开了一种磁存储装置，其包括设置有布线层的层间绝缘膜，形成在层间绝缘膜上的绝缘膜，形成在绝缘膜中的开口，使得布线层暴露于其中，阻挡金属层设置为 为了覆盖开口的内表面，形成在阻挡金属上以便填充开口的下电极和形成在下电极上的TMR元件。

公开(公告)号：US08258592B2

公开(公告)日：2012-09-04

申请号：US12463865

申请日：2009-05-11

申请人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

发明人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/12

摘要： A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.

摘要翻译： 提供一种具有优异的操作特性的MTJ装置的半导体装置及其制造方法。 MTJ装置由层叠结构形成，其通过依次层叠下磁性膜，隧道绝缘膜和上磁性膜而获得。 下部和上部磁性膜含有非结晶或微晶铁硼（CoFeB）作为构成材料。 隧道绝缘膜包含氧化铝（AlOx）作为构成材料。 在上磁性膜上形成CAP层，在CAP层上形成硬掩模。 CAP层包含结晶钌（Ru）作为构成材料的物质，硬掩模含有结晶钽（Ta）作为构成材料的物质。 硬掩模的膜厚大于CAP层的膜厚。

公开(公告)号：US20090237989A1

公开(公告)日：2009-09-24

申请号：US12476536

申请日：2009-06-02

申请人： Yoshinori OKUMURA ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori OKUMURA ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (1/3)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US20080266939A1

公开(公告)日：2008-10-30

申请号：US12213505

申请日：2008-06-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/02

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US07973376B2

公开(公告)日：2011-07-05

申请号：US12549695

申请日：2009-08-28

申请人： Haruo Furuta ,  Ryoji Matsuda ,  Shuichi Ueno ,  Takeharu Kuroiwa

发明人： Haruo Furuta ,  Ryoji Matsuda ,  Shuichi Ueno ,  Takeharu Kuroiwa

IPC分类号： H01L43/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/12

摘要： The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

摘要翻译： 具有包含记忆精度不劣化的TMR膜的存储单元的半导体装置及其制造方法。 在数字线的形成区域的一部分的TMR下电极的平面图中对应的区域选择性地形成TMR元件（TMR膜，TMR上电极）。 TMR上电极由Ta的30-100nm厚度形成，并且在制造过程中也用作硬掩模。 在TMR元件的整个表面和TMR下电极的整个表面上形成由LT-SiN形成的层间绝缘膜，覆盖包括TMR下电极的侧表面的整个表面的层间绝缘膜和 包括LT-SiN。 形成覆盖整个表面并包含SiO 2的层间绝缘膜。

公开(公告)号：US07906346B2

公开(公告)日：2011-03-15

申请号：US12187846

申请日：2008-08-07

申请人： Shuichi Ueno ,  Haruo Furuta ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Shin Hasegawa ,  Shinya Hirano ,  Hiroyuki Chibahara ,  Hiroshi Oshita

发明人： Shuichi Ueno ,  Haruo Furuta ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Shin Hasegawa ,  Shinya Hirano ,  Hiroyuki Chibahara ,  Hiroshi Oshita

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

摘要翻译： 一种制造包括TMR元件的磁存储器件的方法，所述方法包括：形成下布线层的步骤; 在下布线层上形成层间绝缘层的步骤; 在所述层间绝缘层中形成开口以使所述下部布线层露出的步骤; 形成阻挡金属层以使得层间绝缘层和开口的内表面被覆盖的步骤; 在所述阻挡金属层上形成金属层以使得所述开口嵌入的步骤; 抛光步骤，通过使用阻挡金属层作为阻挡层进行研磨来去除阻挡金属层上的金属层，使得形成包含金属层的布线层嵌入开口和阻挡金属层中; 以及在所述布线层上制造TMR元件的元件制造步骤。

公开(公告)号：US20100264501A1

公开(公告)日：2010-10-21

申请号：US12528854

申请日：2008-02-25

申请人： Haruo Furuta ,  Shuichi Ueno ,  Ryoji Matsuda ,  Tatsuta Fukumura ,  Takeharu Kuroiwa ,  Lien-Chang Wang ,  Eugene Chen ,  Yiming Huai

发明人： Haruo Furuta ,  Shuichi Ueno ,  Ryoji Matsuda ,  Tatsuta Fukumura ,  Takeharu Kuroiwa ,  Lien-Chang Wang ,  Eugene Chen ,  Yiming Huai

IPC分类号： H01L29/82 ,  H01L21/02

CPC分类号： H01L43/12 ,  B82Y10/00 ,  H01L27/228

摘要： Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode. Also disclosed is a magnetic storage device comprising an interlayer insulating film provided with a wiring layer, an insulating film formed on the interlayer insulating film, an opening formed in the insulating film so that the wiring layer is exposed therefrom, a barrier metal layer provided so as to cover the inner surface of the opening, a lower electrode formed on the barrier metal so as to fill the opening, and a TMR element formed on the lower electrode.

摘要翻译： 公开了一种制造包括TMR元件的磁存储装置的方法，该方法包括在具有布线层的层间绝缘膜上形成绝缘膜的步骤，用于在绝缘膜上形成开口的开口形成步骤， 布线层暴露于其中，金属层形成步骤用于在绝缘层上形成金属层以使其开口被填充; CMP步骤，用于通过CMP方法在绝缘层上抛光和去除金属层，并形成金属 剩余在开口中的层形成下电极，以及在下电极上形成TMR元件的步骤。 还公开了一种磁存储装置，其包括设置有布线层的层间绝缘膜，形成在层间绝缘膜上的绝缘膜，形成在绝缘膜中的开口，使得布线层暴露于其中，阻挡金属层设置为 为了覆盖开口的内表面，形成在阻挡金属上以便填充开口的下电极和形成在下电极上的TMR元件。