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公开(公告)号：US08450783B2
公开(公告)日：2013-05-28
申请号：US12978805
申请日：2010-12-27
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
IPC分类号： H01L27/085
CPC分类号： H01L29/7869 , G11C16/0425 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/1156 , H01L27/11563 , H01L27/11568 , H01L27/1225 , H01L28/40 , H01L29/78693 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.
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公开(公告)号：US20110156028A1
公开(公告)日：2011-06-30
申请号：US12978805
申请日：2010-12-27
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
IPC分类号： H01L27/108
CPC分类号： H01L29/7869 , G11C16/0425 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/1156 , H01L27/11563 , H01L27/11568 , H01L27/1225 , H01L28/40 , H01L29/78693 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.
摘要翻译： 半导体器件包括源极线，位线，信号线，字线，在源极线和位线之间并联连接的存储器单元，通过开关电连接到源极线和位线的第一驱动器电路 元件，通过开关元件电连接到源极线的第二驱动器电路，电连接到信号线的第三驱动电路，以及电连接到字线的第四驱动电路。 存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。 第二晶体管包括氧化物半导体材料。
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公开(公告)号：US08654566B2
公开(公告)日：2014-02-18
申请号：US13221947
申请日：2011-08-31
IPC分类号： G11C11/24
CPC分类号： G11C11/403 , G11C16/0433 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1156 , H01L27/1225 , H01L29/7869
摘要： The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.
摘要翻译： 半导体器件包括存储单元，其包括第一晶体管，第一晶体管包括第一沟道形成区，第一栅电极以及第一源区和漏区; 第二晶体管，包括设置成与第一源极区域或第一漏极区域中的至少一部分重叠的第二沟道形成区域，第二源极电极，电连接到第一栅极电极的第二漏极电极，以及 第二栅电极; 以及设置在第一晶体管和第二晶体管之间的绝缘层。 在第二晶体管需要处于截止状态的期间中，至少当向第一源极区域或第一漏极区域提供正电位时，向第二栅电极提供负电位。
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公开(公告)号：US08582348B2
公开(公告)日：2013-11-12
申请号：US13195089
申请日：2011-08-01
CPC分类号： G11C16/0408 , G11C11/405 , G11C16/02
摘要： It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a transistor including a first semiconductor material, a transistor including a second semiconductor material that is different from the first semiconductor material, and a capacitor, and a potential switching circuit having a function of supplying a power supply potential to a source line in a writing period. Thus, power consumption of the semiconductor device can be sufficiently suppressed.
摘要翻译： 本发明的目的是提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保持存储的数据，并且对写入操作的数量没有限制。 半导体器件包括多个存储单元，每个存储单元包括包括第一半导体材料的晶体管，包括与第一半导体材料不同的第二半导体材料的晶体管，以及电容器，以及电位切换电路， 在写作期间的电源供应潜力。 因此，可以充分地抑制半导体器件的功耗。
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公开(公告)号：US08451651B2
公开(公告)日：2013-05-28
申请号：US13027543
申请日：2011-02-15
IPC分类号： G11C11/24
CPC分类号： G11C16/0408 , H01L27/11519 , H01L27/11521 , H01L27/1156
摘要： An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device is formed using a material capable of sufficiently reducing the off-state current of a transistor, such as an oxide semiconductor material that is a widegap semiconductor. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor allows data to be held for a long time. In addition, the timing of potential change in a signal line is delayed relative to the timing of potential change in a write word line. This makes it possible to prevent a data writing error.
摘要翻译： 目的是提供一种具有新颖结构的半导体器件，其即使在未被供电且具有无限数量的写周期的情况下也可以保存存储的数据。 使用能够充分降低诸如大孔半导体的氧化物半导体材料的晶体管的截止电流的材料形成半导体器件。 能够充分降低晶体管的截止电流的半导体材料的使用允许长时间保持数据。 此外，信号线中的电位变化的定时相对于写入字线的电位变化的定时被延迟。 这使得可以防止数据写入错误。
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公开(公告)号：US08339837B2
公开(公告)日：2012-12-25
申请号：US13206547
申请日：2011-08-10
IPC分类号： G11C11/24
CPC分类号： G11C16/0433 , G11C11/404
摘要： A semiconductor device with a novel structure and a driving method thereof are provided. A semiconductor device includes a non-volatile memory cell including a writing transistor including an oxide semiconductor, a reading p-channel transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of electric charge is held in the node. In a holding period, the memory cell is brought into a selected state and a source electrode and a drain electrode of the reading transistor are set to the same potential, whereby the electric charge stored in the node is held.
摘要翻译： 提供具有新颖结构的半导体器件及其驱动方法。 一种半导体器件包括：非易失性存储单元，包括包括氧化物半导体的写入晶体管，包括与写入晶体管的半导体材料不同的半导体材料的读取P沟道晶体管，以及电容器。 通过接通写入晶体管将数据写入存储单元，使得电位被提供给写入晶体管的源电极，电容器的一个电极和读取晶体管的栅极电连接的节点，以及 然后关闭写入晶体管，使得节点中保持预定量的电荷。 在保持期间，将存储单元置于选择状态，将读取晶体管的源电极和漏电极设定为相同的电位，由此保存存储在节点中的电荷。
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公开(公告)号：US20120033510A1
公开(公告)日：2012-02-09
申请号：US13197839
申请日：2011-08-04
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C11/403 , G11C11/4087 , H01L27/11517 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in of state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided.
摘要翻译： 目的是提供具有新颖结构的半导体器件，其即使在不提供电力且具有无限数量的写周期的情况下也可以保存存储的数据。 使用包括诸如氧化物半导体的宽带隙半导体的存储单元形成半导体器件。 半导体器件包括具有输出低于用于从存储单元读取数据的参考电位的电位的功能的电位变化电路。 当使用允许存储单元中包括的晶体管的状态电流充分降低的宽带隙半导体时，可以提供能够长期保存数据的半导体器件。
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公开(公告)号：US20120014157A1
公开(公告)日：2012-01-19
申请号：US13175090
申请日：2011-07-01
IPC分类号： G11C5/06
CPC分类号： H01L27/1156 , G11C11/404 , G11C16/0441 , H01L27/1207
摘要： A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.
摘要翻译： 包括在存储单元阵列中的多个存储单元被分成多个块，每个多行。 公共位线通过块中的选择晶体管电连接到分割位线。 一个存储单元包括第一晶体管，第二晶体管和电容器。 第一晶体管包括第一沟道形成区。 第二晶体管包括第二沟道形成区域。 第一沟道形成区域包括与第二沟道形成区域的半导体材料不同的半导体材料。
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公开(公告)号：US20120056647A1
公开(公告)日：2012-03-08
申请号：US13221947
申请日：2011-08-31
IPC分类号： H03K17/00
CPC分类号： G11C11/403 , G11C16/0433 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1156 , H01L27/1225 , H01L29/7869
摘要： The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.
摘要翻译： 半导体器件包括存储单元，其包括第一晶体管，第一晶体管包括第一沟道形成区，第一栅电极以及第一源区和漏区; 第二晶体管，包括设置成与第一源极区域或第一漏极区域中的至少一部分重叠的第二沟道形成区域，第二源极电极，电连接到第一栅极电极的第二漏极电极，以及 第二栅电极; 以及设置在第一晶体管和第二晶体管之间的绝缘层。 在第二晶体管需要处于截止状态的期间中，至少当向第一源极区域或第一漏极区域提供正电位时，向第二栅电极提供负电位。
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公开(公告)号：US20120033485A1
公开(公告)日：2012-02-09
申请号：US13193966
申请日：2011-07-29
IPC分类号： G11C11/24
CPC分类号： G11C16/0408 , G11C11/405 , G11C11/4076 , G11C11/4087 , H01L27/11521 , H01L27/1156 , H01L27/1207
摘要： In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line.
摘要翻译： 在包括位线的m（m为3以上的自然数）字线，源极线，m条信号线，第1〜第m存储器单元和驱动电路的半导体器件中，所述存储单元包括 第一晶体管和第二晶体管，用于存储积聚在电容器中的电荷，第二晶体管包括形成在氧化物半导体层中的沟道。 在半导体装置中，驱动电路使用要输出到第j信号的信号，生成输出到第（j-1）（j为3以上的自然数）信号线的信号 线。
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