公开(公告)号：US08921933B2

公开(公告)日：2014-12-30

申请号：US13111018

申请日：2011-05-19

申请人： Shyi-Yuan Wu ,  Wing-Chor Chan ,  Shih-Chin Lien ,  Cheng-Chi Lin

发明人： Shyi-Yuan Wu ,  Wing-Chor Chan ,  Shih-Chin Lien ,  Cheng-Chi Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/7824 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region.

摘要翻译： 提供半导体结构及其操作方法。 半导体结构包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一沟槽结构和第二栅结构。 第一掺杂区域在衬底中。 第一掺杂区具有第一导电类型。 第二掺杂区域在第一掺杂区域中。 第二掺杂区具有与第一导电类型相反的第二导电类型。 具有第一导电类型的第三掺杂区域在第二掺杂区域中。 第一沟槽结构具有第一栅极结构。 第一栅极结构和第二栅极结构分别位于第二掺杂区域的不同侧。

公开(公告)号：US08482066B2

公开(公告)日：2013-07-09

申请号：US13225189

申请日：2011-09-02

申请人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L31/119

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7824

摘要： A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion.

摘要翻译： 提供了一种半导体器件及其制造方法。 半导体器件包括第一掺杂区，第二掺杂区，电介质结构和栅极结构。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性，并且与第一掺杂区域相邻。 电介质结构包括彼此分离的第一电介质部分和第二电介质部分。 电介质结构形成在第一掺杂区域上。 栅极结构位于与第一电介质部分相邻的第一掺杂区域或第二掺杂区域的一部分上。

公开(公告)号：US08648386B2

公开(公告)日：2014-02-11

申请号：US13222187

申请日：2011-08-31

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/07

CPC分类号： H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

摘要： A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

摘要翻译： 提供其半导体结构及其制造方法以及ESD电路。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区和电阻。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第三掺杂区域具有第一类型的导电性。 第一掺杂区域和第三掺杂区域被第二掺杂区域分开。 电阻器耦合在第二掺杂区域和第三掺杂区域之间。 阳极耦合到第一掺杂区域。 阴极耦合到第三掺杂区域。

公开(公告)号：US20130049067A1

公开(公告)日：2013-02-28

申请号：US13222187

申请日：2011-08-31

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/07 ,  H01L21/331

CPC分类号： H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

摘要： A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

摘要翻译： 提供其半导体结构及其制造方法以及ESD电路。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区和电阻。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第三掺杂区域具有第一类型的导电性。 第一掺杂区域和第三掺杂区域被第二掺杂区域分开。 电阻器耦合在第二掺杂区域和第三掺杂区域之间。 阳极耦合到第一掺杂区域。 阴极耦合到第三掺杂区域。

公开(公告)号：US09029950B2

公开(公告)日：2015-05-12

申请号：US13425221

申请日：2012-03-20

申请人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L29/7816

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括衬底，第一源极/漏极区域，第二源极/漏极区域，第一堆叠结构和第二堆叠结构。 第一源极/漏极区域形成在衬底中。 第二源极/漏极区域形成在衬底中。 第一堆叠结构在第一源极/漏极区域和第二源极/漏极区域之间的衬底上。 第一堆叠结构包括第一介电层和第一介电层上的第一导电层。 第二个堆栈结构是第一个堆叠结构。 第二堆叠结构包括第二电介质层和第二电介质层上的第二导电层。

公开(公告)号：US08610206B2

公开(公告)日：2013-12-17

申请号：US13030815

申请日：2011-02-18

申请人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7835 ,  H01L29/7838

摘要： A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.

摘要翻译： 半导体器件包括源极区域，漏极区域和源极区域与漏极区域之间的漂移区域。 分离栅极设置在漂移区域的一部分上，并且在源极和漏极区域之间。 分离栅极包括由栅极氧化物层隔开的第一和第二栅电极。 自对准RESURF区域设置在栅极和漏极区域之间的漂移区域内。 包括上多晶硅层的PI栅极结构设置在漏极区附近，使得上多晶硅层可以用作形成双RESURF结构的硬掩模，从而允许双RESURF结构的自对准。

公开(公告)号：US20120248574A1

公开(公告)日：2012-10-04

申请号：US13073848

申请日：2011-03-28

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L29/70 ,  H01L21/328

CPC分类号： H01L27/0259

摘要： A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.

摘要翻译： 提供了一种半导体结构及其制造方法及其操作方法。 半导体结构包括第一阱区，第二阱区，第一掺杂区，第二掺杂区，阳极和阴极。 第二阱区域与第一阱区域相邻。 第一掺杂区位于第二阱区上。 第二掺杂区域在第一阱区域上。 阳极耦合到第一掺杂区域和第二阱区域。 阴极耦合到第一阱区和第二掺杂区。 第一阱区和第一掺杂区具有第一导电类型。 第二阱区和第二掺杂区具有与第一导电类型相反的第二导电类型。

公开(公告)号：US20130249007A1

公开(公告)日：2013-09-26

申请号：US13425221

申请日：2012-03-20

申请人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/7816

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括衬底，第一源极/漏极区域，第二源极/漏极区域，第一堆叠结构和第二堆叠结构。 第一源极/漏极区域形成在衬底中。 第二源极/漏极区域形成在衬底中。 第一堆叠结构在第一源极/漏极区域和第二源极/漏极区域之间的衬底上。 第一堆叠结构包括第一介电层和第一介电层上的第一导电层。 第二个堆栈结构是第一个堆叠结构。 第二堆叠结构包括第二电介质层和第二电介质层上的第二导电层。

公开(公告)号：US08519434B2

公开(公告)日：2013-08-27

申请号：US13053920

申请日：2011-03-22

申请人： Hsin-Liang Chen ,  Shou-Lun Tu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Shou-Lun Tu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L23/60

CPC分类号： H01L27/0259 ,  H01L29/1087

摘要： An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection.

摘要翻译： 静电放电（ESD）保护器件可以包括衬底，对应于衬底的第一部分设置并且具有设置在其表面上的两个N +段的N型阱区，邻近于衬底的P型阱区域 具有P +段和N +段的第二部分。 两个N +段可以彼此间隔开，并且每个可以各自与装置的阳极相关联。 N +段可以与器件的阴极相关联。 触点可以位于两个N +段之间的空间中并且连接到P +段。 接触可能形成寄生电容，结合与N +段相关联的寄生电阻，提供高电压ESD保护的自检。

公开(公告)号：US20120241900A1

公开(公告)日：2012-09-27

申请号：US13053920

申请日：2011-03-22

申请人： Hsin-Liang Chen ,  Shou-Lun Tu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Shou-Lun Tu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L27/0259 ,  H01L29/1087

摘要： An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection.

摘要翻译： 静电放电（ESD）保护器件可以包括衬底，对应于衬底的第一部分设置并且具有设置在其表面上的两个N +段的N型阱区，邻近于 具有P +段和N +段的第二部分。 两个N +段可以彼此间隔开，并且每个可以各自与装置的阳极相关联。 N +段可以与器件的阴极相关联。 触点可以位于两个N +段之间的空间中并且连接到P +段。 接触可能形成寄生电容，结合与N +段相关联的寄生电阻，提供高电压ESD保护的自检。