公开(公告)号：US5554863A

公开(公告)日：1996-09-10

申请号：US260331

申请日：1994-06-15

申请人： Sigeyasu Kouzuchi ,  Shuroku Sakurada ,  Takashi Saitoh ,  Hitoshi Komuro

发明人： Sigeyasu Kouzuchi ,  Shuroku Sakurada ,  Takashi Saitoh ,  Hitoshi Komuro

IPC分类号： H01L29/74 ,  H01L29/08 ,  H01L29/744 ,  H01L31/111

CPC分类号： H01L29/744 ,  H01L29/0834

摘要： A gate turn-off thyristor including: an n-type emitter semiconductor layer divided into a plurality of n-type areas; a p-type base semiconductor layer which cooperates with the n-type emitter semiconductor layer to form a first main circular surface; an n-type base semiconductor layer; and a p-type emitter semiconductor layer cooperating with the n-type base semiconductor layer to form a second main circular surface. An outer diameter of the p-type emitter semiconductor layer is smaller than that of the n-type emitter semiconductor layer. A first main electrode put in low resistance contact with the n-type emitter semiconductor layer is formed on the first main surface. A second main electrode put in low resistance contact with the p-type emitter layer and the n-type base semiconductor layer is formed on the second main surface. A control electrode is formed in the p-type base semiconductor on the first main surface. A first electrode plate larger in diameter than the n-type emitter semiconductor layer is connected electrically with the first main electrode. A second electrode plate larger in diameter than the n-type emitter semiconductor layer is connected electrically with the second main electrode.

摘要翻译： 一种栅极截止晶闸管，包括：分为多个n型区域的n型发射极半导体层; p型基极半导体层，与n型发射极半导体层配合形成第一主圆面; n型基极半导体层; 以及与n型基底半导体层配合形成第二主圆形表面的p型发射极半导体层。 p型发射极半导体层的外径小于n型发射极半导体层的外径。 在第一主表面上形成与n型发射极半导体层低电阻接触的第一主电极。 在第二主表面上形成与p型发射极层和n型基极半导体层低电阻接触的第二主电极。 控制电极形成在第一主表面上的p型基极半导体中。 直径大于n型发射极半导体层的第一电极板与第一主电极电连接。 直径大于n型发射极半导体层的第二电极板与第二主电极电连接。

公开(公告)号：US4682198A

公开(公告)日：1987-07-21

申请号：US709139

申请日：1985-03-07

申请人： Shuroku Sakurada ,  Yasuhiko Ikeda

发明人： Shuroku Sakurada ,  Yasuhiko Ikeda

IPC分类号： H01L29/74 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/744

CPC分类号： H01L29/0661 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/744

摘要： A gate turn-off thyristor is provided having a semiconductor substrate, an anode electrode, a cathode electrode and a gate electrode. The semiconductor substrate includes a P emitter layer connected to the anode electrode, an N base layer adjacent to the P emitter layer, a P base layer adjacent to the N base layer and connected to a gate electrode, and an N emitter layer adjacent to the P base layer and connected to the cathode electrode. In order to improve in its current cut-off performance, the semiconductor substrate further includes a P-type layer provided between the P emitter layer and the N base layer and having the impurity concentration lower than that of the N base layer.

摘要翻译： 提供了具有半导体衬底，阳极电极，阴极电极和栅电极的栅极截止晶闸管。 半导体衬底包括连接到阳极电极的P发射极层，与P发射极层相邻的N基极层，与N基极层相邻并连接到栅电极的P基极层和与发射极层相邻的N发射极层 P基极层并连接到阴极电极。 为了提高其截止性能，半导体衬底还包括设置在P发射极层和N基极层之间并且杂质浓度低于N基极层的P型层的P型层。

公开(公告)号：US5635734A

公开(公告)日：1997-06-03

申请号：US402526

申请日：1995-03-10

申请人： Yuji Takayanagi ,  Hideo Kobayashi ,  Shuroku Sakurada ,  Hidekatsu Onose

发明人： Yuji Takayanagi ,  Hideo Kobayashi ,  Shuroku Sakurada ,  Hidekatsu Onose

IPC分类号： H01L21/52 ,  H01L23/051 ,  H01L23/482 ,  H01L29/10 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74

CPC分类号： H01L29/1095 ,  H01L23/051 ,  H01L23/4824 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/13091

摘要： An insulated gate type semiconductor device has a gate electrode which controls current flow between two regions of the same conductivity type in a semiconductor substrate. A main electrode has a first portion contacting a first one of the two regions, a second portion extending above the gate electrode and a third portion providing a raised external contact surface to contact an external electrode. The gate electrode is insulated above and below by insulating films. To prevent damage to the gate electrode and the lower insulating films due to the pressure of the external electrode, there is a supporting insulating layer on the surface of the substrate underlying the contact portion of the main electrode and having a thickness substantially greater than the thickness of the insulating film below the gate electrode and the contact surface is more remote from the substrate than the second portion of said main electrode.

摘要翻译： 绝缘栅型半导体器件具有在半导体衬底中控制相同导电类型的两个区域之间的电流的栅电极。 主电极具有接触两个区域中的第一区域的第一部分，在栅极电极上方延伸的第二部分和提供凸起的外部接触表面以接触外部电极的第三部分。 栅电极通过绝缘膜上下绝缘。 为了防止由于外部电极的压力而对栅电极和下绝缘膜造成的损坏，在主电极的接触部分下面的基板的表面上存在支撑绝缘层，其厚度基本上大于厚度 的绝缘膜，并且接触表面比所述主电极的第二部分更远离衬底。

公开(公告)号：US4868625A

公开(公告)日：1989-09-19

申请号：US71153

申请日：1987-07-08

申请人： Toshihide Ujihara ,  Shuroku Sakurada ,  Tadashi Sakaue ,  Shuji Musha

发明人： Toshihide Ujihara ,  Shuroku Sakurada ,  Tadashi Sakaue ,  Shuji Musha

IPC分类号： H01L29/08 ,  H01L29/74 ,  H01L29/744

CPC分类号： H01L29/0834 ,  H01L29/744

摘要： A gate turn-off (GTO) thyristor has a plurality of unit GTO thyristors of strip-like configuration in a same semiconductor substrate, each unit GTO thyristor being constructed of an N emitter layer, P base layer, N base layer and P emitter layer. The P base and N base layers are shared in common for all the unit GTO thyristors which are formed in a multi-ring configuration. The exposed area of the P emitter layer of a unit GTO thyristor located far from the gate signal input area is made smaller than that of the P emitter layer of a unit GTO thyristor located relatively closer to the gate signal input area.

摘要翻译： 栅极关断（GTO）晶闸管在相同的半导体衬底中具有多个带状结构的单元GTO晶闸管，每个单元GTO晶闸管由N个发射极层，P基极层，N个基极层和P个发射极层 。 对于以多环形式形成的所有单元GTO晶闸管，P基极和N个基极层共同共享。 远离栅极信号输入区域的单元GTO晶闸管的P发射极层的露出面积比位于相对靠近栅极信号输入区域的单位GTO晶闸管的P发射极层的露出面积小。

公开(公告)号：US5051806A

公开(公告)日：1991-09-24

申请号：US385378

申请日：1989-07-27

申请人： Toshihide Ujihara ,  Shuroku Sakurada ,  Tadashi Sakaue ,  Shuji Musha

发明人： Toshihide Ujihara ,  Shuroku Sakurada ,  Tadashi Sakaue ,  Shuji Musha

IPC分类号： H01L29/08 ,  H01L29/74 ,  H01L29/744

CPC分类号： H01L29/0834 ,  H01L29/744

摘要： A gate turn-off (GTO) thyristor has a plurality of unit GTO thyristors of strip-like configuration in a same semiconductor substrate, each unit GTO thyristor being constructed of an N emitter layer, P base layer, N base layer and P emitter layer. The P base and N base layers are shared in common for all the unit GTO thyristors which are formed in a multi-ring configuration. The exposed area of the P emitter layer of a unit GTO thyristor located far from the gate signal input area is made smaller than that of the P emitter layer of a unit GTO thyristor located relatively close to the gate signal input area.

公开(公告)号：US4298881A

公开(公告)日：1981-11-03

申请号：US138085

申请日：1980-04-07

申请人： Shuroku Sakurada ,  Yoichi Nakashima ,  Isao Kojima ,  Hideyuki Yagi ,  Tadaaki Kariya ,  Masayoshi Sugiyama

发明人： Shuroku Sakurada ,  Yoichi Nakashima ,  Isao Kojima ,  Hideyuki Yagi ,  Tadaaki Kariya ,  Masayoshi Sugiyama

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L23/31 ,  H01L29/06 ,  H01L29/74 ,  H01L29/744 ,  H01L29/747

CPC分类号： H01L29/0638 ,  H01L23/3178 ,  H01L29/0661 ,  H01L29/74 ,  H01L29/744 ,  H01L29/747 ,  H01L2924/0002

摘要： This invention concerns a so-called double-moat uni-surface type semiconductor device in which two concentric moats are provided in one main surface of the substrate and the edges of the two pn-junctions for blocking main circuit voltages applied to the device are exposed in the surfaces of the moats. Semiconductor layers having high impurity concentrations and serving as channel stoppers are formed on the semiconductor layers exposed in the one main surface of the substrate, contiguous to the moats and spaced apart from the pn-junctions, each high impurity concentration layer having the same conductivity type as the semiconductor layer on which it is formed. The moats are filled with surface passivating material.

摘要翻译： 本发明涉及一种所谓的双护城河单面型半导体器件，其中两个同心的护城河设置在基板的一个主表面中，并且用于阻挡施加到该器件的主电路电压的两个pn结的边缘暴露 在护城河的表面。 具有高杂质浓度且用作沟道阻挡层的半导体层形成在与基片邻接并与pn结隔开的衬底的一个主表面中露出的半导体层上，每个高杂质浓度层具有相同的导电类型 作为其上形成的半导体层。 护城河充满表面钝化材料。

公开(公告)号：US4786959A

公开(公告)日：1988-11-22

申请号：US308614

申请日：1981-10-05

申请人： Yoshiteru Shimizu ,  Takahiro Nagano ,  Shuroku Sakurada ,  Takehiro Ohta

发明人： Yoshiteru Shimizu ,  Takahiro Nagano ,  Shuroku Sakurada ,  Takehiro Ohta

IPC分类号： H01L29/08 ,  H01L29/74 ,  H01L29/744

CPC分类号： H01L29/0834 ,  H01L29/74 ,  H01L29/744

摘要： A semiconductor substrate of the shape of a disc possesses a first main surface and a second main surface. The semiconductor substrate consists of an emitter layer on the side of the cathode, a second base layer, a first base layer, and an emitter layer on the side of the anode, which are laminated in the order mentioned from the side of the cathode toward the side of the anode. The circumference of the emitter layer on the anode side is short-circuited by an emitter short-circuiting layer on the anode side. On the second main surface is arrayed the emitter layer on the cathode side being divided into a plurality of strip units which are oriented in a radial manner from the center toward the periphery of the semiconductor substrate. The second base layer is exposed on the other portions on the second main surface. The emitter layers on the anode side are provided in the portions where the emitter layers on the cathode side are projected onto the anode side. The emitter short-circuiting layer on the anode side forms a plurality of fan-shaped portions which are oriented in a radial manner from the center toward the periphery of the semiconductor substrate so that the area per unit length in the radial direction of the emitter short-circuiting layer increases from the center toward the periphery. The emitter layers on the anode side and the emitter short-circuiting layers on the anode side are exposed to the first main surface, and are brought into contact with the anode electrodes. The emitter layers on the cathode side are in contact with the cathode electrodes, respectively. The second base layer is in contact with the control electrode, and a lead wire is connected to a central portion of the circular control electrode.

摘要翻译： 盘形状的半导体衬底具有第一主表面和第二主表面。 半导体衬底由阴极侧的发射极层，阳极侧的第二基极层，第一基极层和发射极层构成，它们以从阴极侧向下的顺序层叠 阳极的一侧。 阳极侧的发射极层的周围由阳极侧的发射极短路层短路。 在第二主表面上排列阴极侧的发射极层被分成从半导体衬底的中心向外周向径向定向的多个条状单元。 第二基层暴露在第二主表面上的其它部分上。 阳极侧的发射极层设置在阴极侧的发射极层投射到阳极侧的部分。 阳极侧的发射极短路层形成多个从半导体基板的中心向周向半径方向取向的扇形部，使得发射极的径向的每单位长度的面积短 电路层从中心向周边增加。 阳极侧的发射极层和阳极侧的发射极短路层暴露于第一主表面，并与阳极接触。 阴极侧的发射极层分别与阴极电极接触。 第二基层与控制电极接触，引线与圆形控制电极的中心部连接。

公开(公告)号：US4775916A

公开(公告)日：1988-10-04

申请号：US898597

申请日：1986-08-21

申请人： Shigeyasu Kouzuchi ,  Shuroku Sakurada ,  Tadashi Sakaue ,  Masafumi Ono

发明人： Shigeyasu Kouzuchi ,  Shuroku Sakurada ,  Tadashi Sakaue ,  Masafumi Ono

IPC分类号： H01L21/52 ,  H01L21/58 ,  H01L23/051 ,  H01L23/48 ,  H01L29/74 ,  H01L23/32 ,  H01L23/40

CPC分类号： H01L23/051 ,  H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/1301 ,  H01L2924/351

摘要： A pressure contact semiconductor device has a semiconductor substrate disposed on a metal post electrode through metal electrode plate, an insulating ring engaged with the periphery of the metal post electrode extends to the periphery of the metal electrode plate and is brought into contact therewith at a certain height with a sufficient contact pressure. The semiconductor substrate is positioned precisely with respect to the metal post electrode so that a gate electrode ring is precisely positioned on a gate electrode film formed on the upper surface of the semiconductor substrate.

摘要翻译： 压接半导体器件具有通过金属电极板设置在金属柱电极上的半导体衬底，与金属柱电极的周边接合的绝缘环延伸到金属电极板的周边，并以一定的方式与其接触 高度有足够的接触压力。 半导体衬底相对于金属柱电极精确定位，使得栅电极环精确地定位在形成在半导体衬底的上表面上的栅电极膜上。

公开(公告)号：US4607273A

公开(公告)日：1986-08-19

申请号：US689039

申请日：1985-01-08

申请人： Shuroku Sakurada ,  Hitoshi Matsuzaki ,  Yasuhiko Ikeda ,  Takehiro Ohta

发明人： Shuroku Sakurada ,  Hitoshi Matsuzaki ,  Yasuhiko Ikeda ,  Takehiro Ohta

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L23/482 ,  H01L29/08 ,  H01L29/417 ,  H01L29/74 ,  H01L29/744

CPC分类号： H01L29/41716 ,  H01L23/4824 ,  H01L29/0804 ,  H01L29/0839 ,  H01L29/41708 ,  H01L29/74 ,  H01L2924/0002 ,  Y10S148/14

摘要： A semiconductor device having a semiconductor region of a high impurity concentration which is exposed to one major surface of a semiconductor pellet and has a plurality of split areas, and one main electrode on the major surface which makes low ohmic contact with the semiconductor region and has a bonding pad area for lead connection, comprises the high impurity concentration region underlying the entirety of the main electrode inclusive of the bonding pad, and an insulating film interposed between the bonding pad and the semiconductor region. In a gate turn-off thyristor with a short-circuiting P base region, the semiconductor region constitutes an N emitter region and an area thereof underlying the insulating film prevents the cathode/gate short and current concentration by lateral resistance upon turning off the device by the gate bias. In a bipolar transistor, the semiconductor region constitutes an emitter.

摘要翻译： 一种半导体器件，其具有暴露于半导体芯片的一个主表面并且具有多个分裂区域的高杂质浓度的半导体区域，并且在主表面上的与半导体区域低欧姆接触的一个主电极具有 用于引线连接的接合焊盘区域包括在包括接合焊盘的主电极整体下方的高杂质浓度区域和介于焊盘和半导体区域之间的绝缘膜。 在具有短路P基极区域的栅极截止晶闸管中，半导体区域构成N发射极区域，并且其绝缘膜下方的面积通过横向电阻来防止阴极/栅极的短路和电流集中， 门偏差。 在双极晶体管中，半导体区域构成发射极。

公开(公告)号：US5652467A

公开(公告)日：1997-07-29

申请号：US507989

申请日：1995-07-27

申请人： Hidekatsu Onose ,  Shuroku Sakurada

发明人： Hidekatsu Onose ,  Shuroku Sakurada

IPC分类号： H01L23/48

CPC分类号： H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/30107

摘要： An auxiliary cathode lead is contacted to a cathode buffer electrode which contacts to an unit GTO arranged at the most remote region from a gate pressure contacting portion of a GTO pellet and the push-into effect of the auxiliary cathode current during the turn-off can be remarkably performed. Without inviting bad affects such as the increase in "on" voltage, it is proposed a package structure of a semiconductor which the unit GTO arranged remote from a gate is easily to perform the turn-off. The maximum turn-off current can be heightened, it can easily correspond to the increase in the diameter of the pellet according to the large current of the unit element. Further, a condenser of a snubber circuit as a protection circuit of the unit GTO in a power inverter can be small, and the snubber loss can be lessened.

摘要翻译： 辅助阴极引线与阴极缓冲电极接触，该阴极缓冲电极与GTO颗粒的栅极压力接触部分最远的区域布置的单元GTO接触，并且关断期间辅助阴极电流的推入效应 被显着地执行。 没有引起诸如“开”电压增加的不良影响，提出了一种半导体的封装结构，其中远离栅极的单元GTO易于执行关断。 可以提高最大关断电流，可以根据单元元件的大电流容易地对应于颗粒的直径的增加。 此外，作为功率逆变器中的单元GTO的保护电路的缓冲电路的电容器可以很小，并且可以减小缓冲器损耗。