公开(公告)号：US06927999B2

公开(公告)日：2005-08-09

申请号：US10719265

申请日：2003-11-21

申请人： Soung-Hoon Sim ,  Hyo-Sang Lee ,  Gyu-Hong Kim

发明人： Soung-Hoon Sim ,  Hyo-Sang Lee ,  Gyu-Hong Kim

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30 ,  H01L27/115

CPC分类号： G11C16/0425 ,  G11C16/10 ,  G11C16/30

摘要： An integrated circuit memory device includes a source line and a memory cell array that includes n memory cells that are connected to the source line. The n memory cells are operative to draw current from the source line in response to an n bit data word. A dummy memory cell circuit is operative to draw current from the source line responsive to the n bit data word such that a total current drawn by the memory cell array and the dummy memory cell circuit during a program operation is given by n*a current drawn by one of the n memory cells.

摘要翻译： 集成电路存储器件包括源极线和包括连接到源极线的n个存储器单元的存储单元阵列。 n个存储器单元可操作以响应于n位数据字从源极线引出电流。 虚拟存储单元电路用于响应于n位数据字从源极线抽取电流，使得在编程操作期间由存储器单元阵列和虚拟存储器单元电路绘制的总电流由n * a给出 通过n个存储单元之一。

公开(公告)号：US20120206988A1

公开(公告)日：2012-08-16

申请号：US13358121

申请日：2012-01-25

申请人： Tae-Joong Song ,  Gyu-Hong Kim ,  Jae-Seung Choi ,  Soung-Hoon Sim ,  In-Gyu Park ,  Chan-Ho Lee ,  Hyun-Su Choi ,  Jong-Hoon Jung

发明人： Tae-Joong Song ,  Gyu-Hong Kim ,  Jae-Seung Choi ,  Soung-Hoon Sim ,  In-Gyu Park ,  Chan-Ho Lee ,  Hyun-Su Choi ,  Jong-Hoon Jung

IPC分类号： G11C7/12 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C5/145 ,  G11C7/12

摘要： A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

摘要翻译： 负电压发生器包括可变电容负电压产生单元，开关单元和正电压施加单元。 负电压产生单元包括用于改变负电压被充电的电容的多个耦合电容器。 负电压产生单元根据写入数据的存储体组的行数（大小）选择多个耦合电容器中的至少一个耦合电容器，并将至少一个所选择的耦合电容器充电至负电压。 切换单元响应于数据选择具有互补的第一和第二位线的位线对的一个位线，并且将至少一个选择的耦合电容器连接到所选择的位线。 正电压施加单元将正（高）电压施加到位线对的另一位线。

公开(公告)号：US08934313B2

公开(公告)日：2015-01-13

申请号：US13358121

申请日：2012-01-25

申请人： Tae-Joong Song ,  Gyu-Hong Kim ,  Jae-Seung Choi ,  Soung-Hoon Sim ,  In-Gyu Park ,  Chan-Ho Lee ,  Hyun-Su Choi ,  Jong-Hoon Jung

发明人： Tae-Joong Song ,  Gyu-Hong Kim ,  Jae-Seung Choi ,  Soung-Hoon Sim ,  In-Gyu Park ,  Chan-Ho Lee ,  Hyun-Su Choi ,  Jong-Hoon Jung

IPC分类号： G11C7/12 ,  G11C5/14 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C5/145 ,  G11C7/12

摘要： A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

摘要翻译： 负电压发生器包括可变电容负电压产生单元，开关单元和正电压施加单元。 负电压产生单元包括用于改变负电压被充电的电容的多个耦合电容器。 负电压产生单元根据写入数据的存储体组的行数（大小）选择多个耦合电容器中的至少一个耦合电容器，并将至少一个所选择的耦合电容器充电至负电压。 切换单元响应于数据选择具有互补的第一和第二位线的位线对的一个位线，并且将至少一个选择的耦合电容器连接到所选择的位线。 正电压施加单元将正（高）电压施加到位线对的另一位线。

公开(公告)号：US07788619B2

公开(公告)日：2010-08-31

申请号：US11819389

申请日：2007-06-27

申请人： Soung-Hoon Sim

发明人： Soung-Hoon Sim

IPC分类号： G06F17/50

CPC分类号： G11C5/025 ,  G06F17/5072 ,  G11C8/10 ,  H01L27/0207 ,  H01L27/11898

摘要： A method of compiling a memory for layout by computation includes inputting memory specification, determining a disposition structure of input/output pads with reference to the memory specification, and creating a layout of the memory in accordance with the determined disposition structure of the input/output pads. A memory includes a plurality of memory banks, a plurality of row decoders and a plurality of input/output pads. Each of the plurality of row decoders is arranged between two memory banks adjacent to each other in a row direction. The plurality of row decoders are configured to selectively activate word lines based on row address signals input from an external source. Each row decoder receives row address signals altering a permutation in accordance with a size of the memory banks.

摘要翻译： 通过计算编译用于布局的存储器的方法包括输入存储器规范，参考存储器规范确定输入/输出焊盘的布置结构，以及根据所确定的输入/输出的配置结构来创建存储器的布局 垫 存储器包括多个存储器组，多个行解码器和多个输入/输出焊盘。 多个行解码器中的每一行被布置在行方向上彼此相邻的两个存储体之间。 多个行解码器被配置为基于从外部源输入的行地址信号选择性地激活字线。 每行解码器接收根据存储体的大小改变排列的行地址信号。

公开(公告)号：US08018788B2

公开(公告)日：2011-09-13

申请号：US12382858

申请日：2009-03-25

申请人： Jong-Hoon Jung ,  Soung-Hoon Sim ,  Jung-Min Choi

发明人： Jong-Hoon Jung ,  Soung-Hoon Sim ,  Jung-Min Choi

IPC分类号： G11C5/14

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage line, and the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group.

摘要翻译： 静态存储器件包括连接到内部电压线的位单元和连接在内部电压线和电源电压之间的电源控制电路，其中电源控制电路被配置为将电源电压电平提供给 内部电压线，并且电源控制电路被配置为执行写入辅助功能，其包括在对位单元的写入操作期间使内部电压线浮动，内部电压线响应于模式控制信号的信号而浮置 组。

公开(公告)号：US20090251984A1

公开(公告)日：2009-10-08

申请号：US12382858

申请日：2009-03-25

申请人： Jong-Hoon Jung ,  Soung-Hoon Sim ,  Jung-Min Choi

发明人： Jong-Hoon Jung ,  Soung-Hoon Sim ,  Jung-Min Choi

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage line, and the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group.

摘要翻译： 静态存储器件包括连接到内部电压线的位单元和连接在内部电压线和电源电压之间的电源控制电路，其中电源控制电路被配置为将电源电压电平提供给 内部电压线，并且电源控制电路被配置为执行写入辅助功能，其包括在对位单元的写入操作期间使内部电压线浮动，内部电压线响应于模式控制信号的信号而浮置 组。

公开(公告)号：US20080013376A1

公开(公告)日：2008-01-17

申请号：US11819389

申请日：2007-06-27

申请人： Soung-Hoon Sim

发明人： Soung-Hoon Sim

IPC分类号： G11C11/34

CPC分类号： G11C5/025 ,  G06F17/5072 ,  G11C8/10 ,  H01L27/0207 ,  H01L27/11898

摘要： A method of compiling a memory for layout by computation includes inputting memory specification, determining a disposition structure of input/output pads with reference to the memory specification, and creating a layout of the memory in accordance with the determined disposition structure of the input/output pads. A memory includes a plurality of memory banks, a plurality of row decoders and a plurality of input/output pads. Each of the plurality of row decoders is arranged between two memory banks adjacent to each other in a row direction. The plurality of row decoders are configured to selectively activate word lines based on row address signals input from an external source. Each row decoder receives row address signals altering a permutation in accordance with a size of the memory banks.

摘要翻译： 通过计算编译用于布局的存储器的方法包括输入存储器规范，参考存储器规范确定输入/输出焊盘的布置结构，以及根据所确定的输入/输出的配置结构来创建存储器的布局 垫 存储器包括多个存储器组，多个行解码器和多个输入/输出焊盘。 多个行解码器中的每一行被布置在行方向上彼此相邻的两个存储体之间。 多个行解码器被配置为基于从外部源输入的行地址信号选择性地激活字线。 每行解码器接收根据存储体的大小改变排列的行地址信号。

公开(公告)号：US07020024B2

公开(公告)日：2006-03-28

申请号：US10403468

申请日：2003-03-31

申请人： Soung-Hoon Sim

发明人： Soung-Hoon Sim

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C8/00

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0425

摘要： A flash memory can operate by providing a first voltage level from a row decoder to a wordline associated with a cell of a flash memory device. An address provided to the row decoder is decoded during an erase mode operation of the flash memory. The first voltage level is increased to a second voltage level provided from the row decoder to the wordline responsive to determining that the wordline is not selected by the address during the erase mode operation.