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    Synchronous integrated memory
    1.
    发明授权
    Synchronous integrated memory 有权
    同步集成存储器

    公开(公告)号：US06275445B1

    公开(公告)日：2001-08-14

    申请号：US09617649

    申请日：2000-07-17

    申请人： Stefan Dietrich ,  Peter Schrögmeier ,  Torsten Partsch ,  Christian Weis

    发明人： Stefan Dietrich ,  Peter Schrögmeier ,  Torsten Partsch ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1078

    摘要： A memory has data lines through which data connections are connected to groups of memory cells via a synchronizing unit. The synchronizing unit is disposed adjacent to the cell group and has a clock input to which an internal clock signal is fed. In the event of a write access to the memory, the synchronizing unit synchronizes with the internal clock signal data signals that are fed via the data connections and are synchronous with an external clock signal.

    摘要翻译： 存储器具有数据线，数据连接经由同步单元连接到存储器单元组。 同步单元被布置成与单元组相邻并且具有被馈送内部时钟信号的时钟输入。 在对存储器进行写访问的情况下，同步单元与经由数据连接馈送的内部时钟信号数据信号同步，并与外部时钟信号同步。

    Method and circuit configuration for read-write mode control of a synchronous memory
    8.
    发明授权
    Method and circuit configuration for read-write mode control of a synchronous memory 有权
    用于同步存储器的读写模式控制的方法和电路配置

    公开(公告)号：US06359832B2

    公开(公告)日：2002-03-19

    申请号：US09773222

    申请日：2001-01-31

    申请人： Stefan Dietrich ,  Sabine Schöniger ,  Peter Schrögmeier ,  Christian Weis

    发明人： Stefan Dietrich ,  Sabine Schöniger ,  Peter Schrögmeier ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C7/12 ,  G11C11/4094

    摘要： A read-write mode control method is described in which a waiting time during a reading process can be shortened by conducting a read instruction with auto-precharging in a first circuit part. The first circuit part is separate from a second circuit part used for conducting the write instruction, since a memory controller does not need to insert any wait cycles between a write instruction and an associated activate signal.

    摘要翻译： 描述了一种读写模式控制方法，其中可以通过在第一电路部分中进行具有自动预充电的读取指令来缩短读取处理期间的等待时间。 第一电路部分与用于执行写指令的第二电路部分分开，因为存储器控制器不需要在写指令和相关联的激活信号之间插入任何等待周期。

    Integrated circuit having a command decoder
    9.
    发明授权
    Integrated circuit having a command decoder 有权
    具有命令解码器的集成电路

    公开(公告)号：US06404699B1

    公开(公告)日：2002-06-11

    申请号：US09603742

    申请日：2000-06-26

    申请人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Schöniger ,  Christian Weis

    发明人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Schöniger ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/22 ,  G11C7/1045 ,  G11C11/4076

    摘要： The integrated circuit has an activation decoder whose outputs are connected to the inputs of a command decoder. When an activation signal is at a first logic level, the activation decoder produces at its outputs a command supplied to it from command inputs. When the activation signal is at a second logic level, the activation decoder produces a deactivation command at its outputs irrespective of the command supplied to it from the command inputs. The command decoder does not activate any of its outputs when the deactivation command is being supplied to its inputs. The command decoder activates one of its outputs in each case when a different command is supplied to its inputs.

    摘要翻译： 集成电路具有激活解码器，其输出端连接到命令解码器的输入端。 当激活信号处于第一逻辑电平时，激活解码器在其输出端产生从命令输入提供给它的命令。 当激活信号处于第二逻辑电平时，激活解码器在其输出处产生停用命令，而与从命令输入提供给其的命令无关。 当向其输入提供停用命令时，命令解码器不会激活其任何输出。 当向其输入提供不同的命令时，命令解码器在每种情况下激活其一个输出。

    Integrated memory with a block writing function and global amplifiers requiring less space
    10.
    发明授权
    Integrated memory with a block writing function and global amplifiers requiring less space 有权
    具有块写入功能的集成存储器和需要较少空间的全局放大器

    公开(公告)号：US06351419B1

    公开(公告)日：2002-02-26

    申请号：US09580986

    申请日：2000-05-30

    申请人： Stefan Dietrich ,  Peter Schrögmeier ,  Sabine Schöniger ,  Christian Weis

    发明人： Stefan Dietrich ,  Peter Schrögmeier ,  Sabine Schöniger ,  Christian Weis

    IPC分类号： G11C700

    CPC分类号： G11C7/18 ,  G11C7/06

    摘要： An integrated memory has a first operating mode, in which, during each write access, only one of the two global amplifiers is active and transmits a datum via one of the local amplifiers to the corresponding bit line. Moreover, the memory has a second operating mode, in which, during each write access, both global amplifiers are simultaneously active and transmit a common datum via in each case at least one of the local amplifiers to the corresponding bit lines.

    摘要翻译： 集成存储器具有第一操作模式，其中在每个写入期间，两个全局放大器中只有一个是有源的，并且通过一个本地放大器将数据发送到对应的位线。 此外，存储器具有第二操作模式，其中在每个写入期间，两个全局放大器同时被激活，并且在每个情况下将至少一个本地放大器的公共数据通路传送到对应的位线。