公开(公告)号：US07915667B2

公开(公告)日：2011-03-29

申请号：US12137388

申请日：2008-06-11

申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

IPC分类号： H01L29/792 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

公开(公告)号：US07427548B2

公开(公告)日：2008-09-23

申请号：US11170187

申请日：2005-06-29

申请人： Stephan Riedel ,  Stefano Parascandola

发明人： Stephan Riedel ,  Stefano Parascandola

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L29/66833

摘要： A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling (7) is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks (8) are formed.

摘要翻译： 在硅衬底（1）的主表面上施加包括下约束层（2），电荷俘获层（3）和上限制层（4）的存储层序列。 通过光刻步骤，蚀刻彼此间隔一定距离的平行沟槽，以界定有效面积。 沟槽填充（7）通过介电材料的生长或沉积或通过基底材料的选择性氧化来施加。 在去除外围区域中的电荷捕获层序列并且为寻址电路的晶体管提供的栅极电介质材料的沉积形成字线叠层（8）之后。

公开(公告)号：US07288812B2

公开(公告)日：2007-10-30

申请号：US10857637

申请日：2004-05-27

申请人： Stephan Riedel

发明人： Stephan Riedel

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0491 ,  H01L27/115

摘要： Insulation regions in the manner of STI isolations, which run transversely with respect to the word lines, isolate the source/drain regions of adjacent memory cells. Metallic bit lines are applied on the top side and patterned for example along zigzag lines such that the source/drain regions of a memory transistor which are contact-connected by the bit lines are in each case electrically connected by two mutually adjacent bit lines.

摘要翻译： 绝缘区域以相对于字线横向延伸的STI隔离的方式隔离相邻存储器单元的源极/漏极区域。 金属位线施加在顶侧，并且例如沿着之字形线图案化，使得通过位线接触连接的存储晶体管的源极/漏极区域在每种情况下都由两个相互相邻的位线电连接。

公开(公告)号：US20060114724A1

公开(公告)日：2006-06-01

申请号：US11000335

申请日：2004-11-30

申请人： Stephan Riedel ,  Elard Kamienski ,  Norbert Schulze

发明人： Stephan Riedel ,  Elard Kamienski ,  Norbert Schulze

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C16/0466 ,  H01L27/1203

摘要： A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.

摘要翻译： 非挥发性半导体存储器包括具有衬底区域，至少一个字线，布置在多个扇区中的多个非易失性存储单元的衬底，并且还包括第一掺杂类型的第一阱，电绝缘元件和开关 元素。 每个扇区包括通常布置在相应的第一阱中的多个非易失性存储单元。 所述至少一个字线电连接所述多个扇区中的一组扇区的存储单元。 第一个阱通过电绝缘元件从衬底区域和彼此分离。 每个第一阱连接到相应的开关元件，并且半导体存储器被构造成使得每个第一阱通过相应的开关元件可偏置到预定电位。 此外，提供了用于操作上述非易失性半导体存储器的方法。

公开(公告)号：US09039003B2

公开(公告)日：2015-05-26

申请号：US14199252

申请日：2014-03-06

申请人： Toni Egli ,  Stephan Riedel

发明人： Toni Egli ,  Stephan Riedel

IPC分类号： B41F13/64 ,  B65H29/51 ,  B65H39/02 ,  B65H39/105 ,  B65H39/00

CPC分类号： B41F13/64 ,  B65H29/51 ,  B65H39/00 ,  B65H39/02 ,  B65H39/105 ,  B65H2301/141 ,  B65H2301/22 ,  B65H2301/4213 ,  B65H2301/4312 ,  B65H2404/42 ,  B65H2404/652 ,  B65H2405/541 ,  B65H2511/11 ,  B65H2513/42 ,  B65H2701/1131 ,  B65H2220/01 ,  B65H2220/02

摘要： An apparatus for processing sheets of different formats, the apparatus including a feeding device that feed sheets of different formats in a feeding direction one behind the other, and at a certain conveying speed, at least two collecting drums disposed downstream of the feeding device, the at least two collecting drums having cylindrical lateral surfaces that rotate about an axis of rotation, securing means for temporarily securing the fed sheets on a circumference of the at least two collecting drums, a drive device that drives the collecting drums in rotation at a circumferential speed that corresponds to the conveying speed of the feeding device, and a sensing device for sensing the sheets of different formats moving past is arranged along the conveying path and senses the leading edge of the sheets of different formats, as seen in the feeding direction, or markings applied to the sheets of different formats.

摘要翻译： 一种用于处理不同格式的片材的装置，该装置包括一个馈送装置，该馈送装置沿一个接一个的馈送方向以一定的传送速度馈送不同格式的片材，至少两个设置在馈送装置下游的收集鼓， 至少两个收集鼓，其具有围绕旋转轴线旋转的圆柱形侧表面;用于将进给的片材临时固定在至少两个收集鼓的圆周上的固定装置，驱动装置，其以圆周速度旋转收集鼓 对应于进给装置的传送速度，以及用于感测移动过去的不同格式的纸张的感测装置沿着传送路径布置，并且感测从进给方向看不同格式的纸张的前缘，或者 标记应用于不同格式的纸张。

公开(公告)号：US08708326B2

公开(公告)日：2014-04-29

申请号：US13427154

申请日：2012-03-22

申请人： Toni Egli ,  Stephan Riedel

发明人： Toni Egli ,  Stephan Riedel

IPC分类号： B41F13/64

CPC分类号： B41F13/64 ,  B65H29/51 ,  B65H39/00 ,  B65H39/02 ,  B65H39/105 ,  B65H2301/141 ,  B65H2301/22 ,  B65H2301/4213 ,  B65H2301/4312 ,  B65H2404/42 ,  B65H2404/652 ,  B65H2405/541 ,  B65H2511/11 ,  B65H2513/42 ,  B65H2701/1131 ,  B65H2220/01 ,  B65H2220/02

摘要： Sheets of different formats, i.e. of different format lengths, are transported in a feeding direction one behind the other; and at a certain conveying speed, to at least two collecting drums, which have essentially cylindrical lateral surfaces. Each of these collecting drums is driven about an axis of rotation at a circumferential speed, which corresponds essentially to the feeding speed of the sheets. The first incoming sheet is secured temporarily on one of the collecting drums, while the following, second sheet is secured temporarily on the other collecting drum. At a suitable point in time, the two sheets secured on the collecting drums are detached from the collecting drums and brought together with the third fed sheet to form a sub-product or end product.

摘要翻译： 不同格式，即不同格式长度的纸张沿进给方向一个接一个地传送; 并以一定的输送速度传送到至少两个具有基本上圆柱形侧表面的收集​​鼓。 这些收集鼓中的每一个围绕旋转轴以圆周速度驱动，其基本上对应于片材的进给速度。 第一进纸片被临时固定在一个收集鼓上，而下面的第二纸张暂时固定在另一个收集鼓上。 在合适的时间点，固定在收集鼓上的两个片材与收集鼓分离，并与第三个送入的片材一起形成副产品或最终产品。

公开(公告)号：US08116142B2

公开(公告)日：2012-02-14

申请号：US11220872

申请日：2005-09-06

申请人： Stephan Riedel ,  Boaz Eitan

发明人： Stephan Riedel ,  Boaz Eitan

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/16

摘要： The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element may be located and/or activated across two bit-lines defining a given column of cells, where one or a subset of cells from the column may be undergoing an erase operation or procedure. The shunting element may be located, and/or activated, at some distance from the two bit-lines defining the given column of cells, and the shunting element may be electrically connected to the bit-lines defining the column through select transistors and/or through global bit-lines.

摘要翻译： 本发明是用于擦除非易失性存储单元的方法，电路和系统。 可以在连接一个或多个NVM单元被擦除的位线之间引入和/或激活分流元件（例如晶体管）。 分流元件可以定义和/或激活跨定义单元的给定列的两个位线，其中来自列的一个或一个子集的子集可能经历擦除操作或过程。 分流元件可以位于距离限定给定列的单元的两个位线一定距离处，并且/或被激活，并且分流元件可以通过选择晶体管和/或定向元件电连接到限定该列的位线 通过全局位线。

公开(公告)号：US20070075381A1

公开(公告)日：2007-04-05

申请号：US11241878

申请日：2005-09-30

申请人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

发明人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11565 ,  H01L27/11568

摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

摘要翻译： 位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。 横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。 在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。 在阻塞区域之间，字线正常布置在位线上。

公开(公告)号：US20060091424A1

公开(公告)日：2006-05-04

申请号：US10978216

申请日：2004-10-29

申请人： Matthias Strassburg ,  Stephan Riedel

发明人： Matthias Strassburg ,  Stephan Riedel

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： Semiconductor Device And Method Of Producing A Semiconductor Device A semiconductor device comprises a memory cell (160) including a transistor body (150) having a top surface (111) and including a first doping area (10a) and a second doping area (10b) with a channel region (110) in between. The memory cell (160) further includes a gate electrode (3a) arranged above the channel region (110) and separated therefrom by a dielectric layer (2a). An oxide-nitride-oxide layer (66) has first portions (661) and second portions (662). The first portions (661) of the oxide-nitride-oxide layer (66) are arranged above at least parts of the first and second doping areas (10a, 10b) and are substantially parallel to the top surface (111) of the transistor body (150). The second portions (662) of the oxide-nitride-oxide layer (66) are adjacent to the gate electrode (3a) and extend in a direction not substantially parallel to the top surface (111) of the transistor body (150).

摘要翻译： 半导体器件和半导体器件的制造方法半导体器件包括存储单元（160），其包括具有顶表面（111）并包括第一掺杂区域（10a）和第二掺杂区域（10）的晶体管本体（150） b）在其间具有通道区域（110）。 存储单元（160）还包括布置在沟道区（110）上方并通过电介质层（2a）分离的栅电极（3a）。 氧化物 - 氧化物 - 氧化物层（66）具有第一部分（661）和第二部分（662）。 氧化物 - 氮化物 - 氧化物层（66）的第一部分（661）布置在第一和第二掺杂区域（10a，10b）的至少一部分上方并且基本上平行于 晶体管体（150）。 氧化物 - 氧化物 - 氧化物层（66）的第二部分（662）与栅电极（3a）相邻并且在基本上不平行于晶体管本体（150）的顶表面（111）的方向上延伸。

公开(公告)号：US20060054979A1

公开(公告)日：2006-03-16

申请号：US11010643

申请日：2004-12-13

申请人： Philipp Kratzert ,  Norbert Schulze ,  Juerg Haufe ,  Roland Haberkern ,  Stephan Riedel ,  Patrick Haibach

发明人： Philipp Kratzert ,  Norbert Schulze ,  Juerg Haufe ,  Roland Haberkern ,  Stephan Riedel ,  Patrick Haibach

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L29/6656 ,  H01L29/66833

摘要： A method for fabricating a drain/source path is provided, in which essentially firstly a nitride layer is applied, on which a TEOS layer is then patterned. The patterning is effected in a simplified manner by virtue of the fact that the nitride layer acts as an etching stop layer during the etching away of the TEOS layer.

摘要翻译： 提供了一种用于制造漏极/源极路径的方法，其中基本上首先施加氮化物层，然后在其上构图TEOS层。 由于在TEOS层蚀刻期间氮化物层作为蚀刻停止层的事实，以简化的方式实现图案化。