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    Integrated circuits having a contact region and methods for manufacturing the same
    1.
    发明授权
    Integrated circuits having a contact region and methods for manufacturing the same 有权
    具有接触区域的集成电路及其制造方法

    公开(公告)号：US07915667B2

    公开(公告)日：2011-03-29

    申请号：US12137388

    申请日：2008-06-11

    申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    IPC分类号： H01L29/792 ,  H01L29/788 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

    Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same
    2.
    发明申请
    Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same 有权
    具有接触区域的集成电路及其制造方法

    公开(公告)号：US20090309152A1

    公开(公告)日：2009-12-17

    申请号：US12137388

    申请日：2008-06-11

    申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

    DRAM memory cell
    3.
    发明授权
    DRAM memory cell 失效
    DRAM存储单元

    公开(公告)号：US07368752B2

    公开(公告)日：2008-05-06

    申请号：US10839800

    申请日：2004-05-06

    申请人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    发明人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    IPC分类号： H01L27/108 ,  H01L29/12 ,  H01L31/112

    CPC分类号： H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

    摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

    摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

    Fin field effect transistor memory cell
    7.
    发明申请
    Fin field effect transistor memory cell 审中-公开
    Fin场效应晶体管存储单元

    公开(公告)号：US20060001058A1

    公开(公告)日：2006-01-05

    申请号：US11157496

    申请日：2005-06-20

    申请人： Lars Dreeskornfeld ,  Jessica Hartwich ,  Franz Hofmann ,  Johannes Kretz ,  Michael Specht

    发明人： Lars Dreeskornfeld ,  Jessica Hartwich ,  Franz Hofmann ,  Johannes Kretz ,  Michael Specht

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/42384 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

    摘要： A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region, and a word line region on at least one part of the charge storage layer. The charge storage layer is set up such that electrical charge carriers can be selectively introduced into the charge storage layer or be removed therefrom by applying predetermined electrical potentials to the fin field effect transistor memory cell.

    摘要翻译： 具有第一和第二源极/漏极区域的栅极场效应晶体管存储单元，栅极区域，具有在第一和第二源极/漏极区域之间的沟道区域的半导体鳍片，被配置为俘获层的电荷存储层， 至少部分地在栅极区域上，以及电荷存储层的至少一部分上的字线区域。 电荷存储层被设置成使得电荷载流子可以选择性地引入电荷存储层中，或者通过向鳍式场效应晶体管存储单元施加预定的电位而将其移除。

    Integrated circuit array
    8.
    发明申请
    Integrated circuit array 审中-公开
    集成电路阵列

    公开(公告)号：US20050224888A1

    公开(公告)日：2005-10-13

    申请号：US11116139

    申请日：2005-04-27

    申请人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Honlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Luyken ,  Wolfgang Roesner ,  Thomas Schulz ,  Michael Specht

    发明人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Honlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Luyken ,  Wolfgang Roesner ,  Thomas Schulz ,  Michael Specht

    IPC分类号： G11C13/02 ,  H01L29/78 ,  H01L51/00 ,  H01L51/30 ,  H01L29/76

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

    摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.

    摘要翻译： 集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。 阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域 和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件 每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层 门区域。

    Semiconductor memory with vertical memory transistors and method for fabricating it
    9.
    发明申请
    Semiconductor memory with vertical memory transistors and method for fabricating it 有权
    具有垂直存储晶体管的半导体存储器及其制造方法

    公开(公告)号：US20050199942A1

    公开(公告)日：2005-09-15

    申请号：US11073205

    申请日：2005-03-05

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Luyken ,  Thomas Schulz ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Luyken ,  Thomas Schulz ,  Michael Specht

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792

    CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

    摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

    摘要翻译： 本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。 半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。 半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。 形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。 该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层， 以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。