公开(公告)号：US06967370B2

公开(公告)日：2005-11-22

申请号：US10785087

申请日：2004-02-25

申请人： Stephan Schröder ,  Joerg Vollrath ,  Tobias Hartner

发明人： Stephan Schröder ,  Joerg Vollrath ,  Tobias Hartner

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L21/76838 ,  H01L27/0207 ,  H01L27/10885 ,  H01L27/10888

摘要： An integrated semiconductor circuit can have memory cells, which can be read by word lines and bit lines. Two mutually adjacent bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitors, which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts, additional contact structures which lead past the word lines and represent dummy contacts can be provided. The additional parasitic capacitances produced by the dummy contact alter the electrical potential of the respective reference bit line at the signal amplifier like the parasitic capacitances of activated bit lines, as a result of which the measured differential potential can be corrected with respect to the parasitic effects.

摘要翻译： 集成半导体电路可以具有能够被字线和位线读取的存储单元。 每种情况下两个相互相邻的位线连接到同一信号放大器的输入端。 为了补偿在图案化字线和相邻位线触点之间的薄侧壁绝缘处产生的寄生电容器，可以提供通过字线并代表虚拟触点的附加接触结构。 由虚拟触点产生的额外的寄生电容改变了信号放大器处的相应参考位线的电位，就像激活的位线的寄生电容一样，由此可以相对于寄生效应来校正所测量的微分电位 。

公开(公告)号：US06998664B2

公开(公告)日：2006-02-14

申请号：US10787119

申请日：2004-02-27

申请人： Joerg Vollrath ,  Stephan Schröder ,  Tobias Hartner

发明人： Joerg Vollrath ,  Stephan Schröder ,  Tobias Hartner

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated semiconductor circuit includes a cell array having memory cells which can be read by word lines and bit lines. Two bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitances which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts which connect the bit lines located at a higher level to the active regions located at a deeper level, two additional word lines and dummy contacts of the bit lines are dummy contacts lead past this additional word lines. The additional parasitic capacitances produced by the dummy contacts alter the electrical potential of the respective reference bit line at the signal amplifier in the same way as the parasitic capacitances of activated bit lines, as a result of which the measured differential potential is corrected with respect to the parasitic effects.

摘要翻译： 集成半导体电路包括具有可由字线和位线读取的存储单元的单元阵列。 每种情况下的两个位线连接到相同信号放大器的输入。 为了补偿在图案化字线和相邻位线触点之间的薄侧壁绝缘处产生的寄生电容，其将位于较高电平的位线连接到位于较深电平的有源区，两个附加字线和虚拟触点 的位线是虚拟触点通过这个附加字线。 由虚拟触点产生的附加寄生电容以与激活的位线的寄生电容相同的方式改变信号放大器处的各个参考位线的电位，结果是相对于 寄生效应。

公开(公告)号：US06900626B2

公开(公告)日：2005-05-31

申请号：US10736506

申请日：2003-12-17

申请人： Manfred Pröll ,  Ralf Schneider ,  Stephan Schröder ,  Joerg Vollrath

发明人： Manfred Pröll ,  Ralf Schneider ,  Stephan Schröder ,  Joerg Vollrath

IPC分类号： G05F3/30 ,  G05F3/08

CPC分类号： G05F3/30

摘要： A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit is downstream from an impedance converter and downstream a voltage generator. The bandgap reference circuit and the impedance converter on the one hand and the voltage generator on the other hand are connected to different reference ground potential line. The impedance converter contains a charge pump circuit to provide increased control potential, which drives the voltage generator. The voltage generator in contrast produces a reduced output potential. The influence of any voltage drop on that reference ground potential line to which the voltage generator is connected in the output potential is thus likewise reduced.

摘要翻译： 电压发生器装置提供具有高电流驱动能力的大部分恒定的输出电压。 带隙参考电路在阻抗转换器的下游，电压发生器的下游。 另一方面，带隙参考电路和阻抗转换器和电压发生器连接到不同的参考地电位线。 阻抗转换器包含电荷泵电路，以提供增加的控制电位，驱动电压发生器。 相反，电压发生器产生降低的输出电位。 因此，电压发生器连接到输出电位的参考地电位线上的任何电压降的影响同样降低。

公开(公告)号：US06816094B2

公开(公告)日：2004-11-09

申请号：US10619290

申请日：2003-07-15

申请人： Joerg Vollrath ,  Stephan Schröder

发明人： Joerg Vollrath ,  Stephan Schröder

IPC分类号： H03M900

CPC分类号： G11C7/1057 ,  G11C7/1051

摘要： A circuit configuration for the bit-parallel outputting the bits of a data word includes at least two signal lines for feeding the data signals representing the bits of the data word to driver stages and to a reference circuit. Further driver stages are connected in parallel with the driver stages and have inputs connected to the control device. The control device establishes the signal states of the data signals to be transferred on each signal line and generates a control signal depending on the type and number of the signal state changes of bit sequences to be transferred. It is possible to drive the driver stages that assigned to the signal line for which a signal state change is present.

摘要翻译： 用于比特并行输出数据字的位的电路配置包括用于将表示数据字的位的数据信号馈送到驱动器级的至少两条信号线和参考电路。 其他驱动级与驱动级并联，并具有连接到控制装置的输入。 控制装置建立要在每个信号线上传送的数据信号的信号状态，并根据要传送的位序列的信号状态变化的类型和数量产生控制信号。 可以驱动分配给信号状态改变的信号线的驱动级。

公开(公告)号：US06927557B2

公开(公告)日：2005-08-09

申请号：US10736507

申请日：2003-12-17

申请人： Manfred Pröll ,  Stephan Schröder ,  Joerg Vollrath ,  Ralf Schneider

发明人： Manfred Pröll ,  Stephan Schröder ,  Joerg Vollrath ,  Ralf Schneider

IPC分类号： G05F1/46 ,  G05F3/04

CPC分类号： G05F1/465

摘要： A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit drives a voltage generator on the output side, if necessary via an impedance converter. The bandgap reference circuit and the impedance converter on the one hand, and the voltage generator on the other hand, are connected to different reference ground potential lines. The voltage generator on the output side is preceded by a correction circuit, which corrects for the voltage drop on that reference ground potential line to which the output-side voltage generator is connected. The voltage generator arrangement is suitable for a greater integration density.

摘要翻译： 电压发生器装置提供具有高电流驱动能力的大部分恒定的输出电压。 如果需要，带隙参考电路驱动输出侧的电压发生器，通过阻抗转换器。 一方面，带隙参考电路和阻抗转换器以及另一方面的电压发生器连接到不同的参考地电位线。 输出侧的电压发生器前面有一个校正电路，用于校正输出侧电压发生器连接到的参考地电位线上的电压降。 电压发生器装置适合于更大的集成密度。

公开(公告)号：US06853214B2

公开(公告)日：2005-02-08

申请号：US10619014

申请日：2003-07-11

申请人： Stephan Schröder ,  Joerg Vollrath

发明人： Stephan Schröder ,  Joerg Vollrath

IPC分类号： H03F3/21 ,  H03F3/45 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/018585 ,  H03F3/211 ,  H03F3/45475 ,  H03K19/00384

摘要： A circuit configuration has a first driver stage for feeding in an input signal and for outputting an amplified signal. A second driver stage, which is connected in parallel with the first driver stage, is fed, on the input side, both the input signal and a control signal from a reference circuit connected upstream. The reference circuit compares the feedback level of an output signal, which level is present at one of its inputs, with the level of the input signal present at its other input and generates the control signal for driving the driver stage in the event that the level of the output signal is lower than the level of the input signal. As a result, the driver stage is connected for additional amplification of the input signal.

摘要翻译： 电路配置具有用于馈送输入信号并输出​​放大信号的第一驱动级。 与第一驱动级并联连接的第二驱动级在输入侧馈送输入信号和来自上游连接的参考电路的控制信号。 参考电路将输出信号的一个输入信号的反馈电平与存在于其另一个输入端的输入信号的电平进行比较，并产生用于驱动驱动级的控制信号， 的输出信号低于输入信号的电平。 结果，连接驱动级以进一步放大输入信号。

公开(公告)号：US07402859B2

公开(公告)日：2008-07-22

申请号：US11079884

申请日：2005-03-15

申请人： Joerg Vollrath ,  Marcin Gnat ,  Ralf Schneider ,  Stephan Schroeder

发明人： Joerg Vollrath ,  Marcin Gnat ,  Ralf Schneider ,  Stephan Schroeder

IPC分类号： H01L27/108 ,  H01L21/336

CPC分类号： H01L29/78696 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78618

摘要： A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.

摘要翻译： 场效应半导体包括在半导体层的表面上彼此相邻布置的半导体层中具有表面的第一和第二半导体区域的半导体层，在第一半导体区域和第二半导体区域之间的绝缘层 半导体区域，半导体层的表面上的半导体条，该半导体条与第一半导体区域和第二半导体区域重叠，并与其邻接。 至少在绝缘层的区域中，栅极与半导体条重叠。 栅介质将栅极与半导体条绝缘在第一半导体区和第二半导体区之间。 半导体条和栅极形成为使得半导体条以第一预定栅极电压电绝缘并且在第二预定栅极电压下导电。

公开(公告)号：US20080151594A1

公开(公告)日：2008-06-26

申请号：US11958639

申请日：2007-12-18

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C17/16 ,  G11C17/165 ,  G11C29/006 ,  G11C29/56 ,  G11C2207/2254

摘要： A semiconductor device with a plurality of one time programmable elements and to a method for programming a semiconductor device, and to a method for operating a semiconductor device is disclosed. One embodiment provides a method for programming a semiconductor device comprising a plurality of one time programmable elements that form a group of one time programmable elements. The one time programmable elements of the group are left in a non-programmed state if a first information is to be stored by the group. A first one time programmable element of the group is programmed if a second information differing from the first information is to be stored by the group.

摘要翻译： 公开了一种具有多个一次可编程元件的半导体器件和用于编程半导体器件的方法以及用于操作半导体器件的方法。 一个实施例提供了一种用于编程半导体器件的方法，该半导体器件包括形成一组一次可编程元件的多个一次可编程元件。 如果要由组存储第一信息，则该组的一次可编程元件保持在非编程状态。 如果组中存储与第一信息不同的第二信息，则对该组的第一个一次可编程元件进行编程。

公开(公告)号：US07196537B2

公开(公告)日：2007-03-27

申请号：US11092963

申请日：2005-03-30

申请人： Aurel von Campenhausen ,  Joerg Vollrath ,  Ralf Schneider ,  Marcin Gnat

发明人： Aurel von Campenhausen ,  Joerg Vollrath ,  Ralf Schneider ,  Marcin Gnat

IPC分类号： G01R31/26

CPC分类号： G11C29/1201 ,  G01R31/275 ,  G01R31/2884 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/5002

摘要： An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.

摘要翻译： 集成电路包括电路部件，第一控制电路和可切换电阻网络。 输入电压被馈送到输入侧的电路部件。 由第一控制电路产生的控制信号被馈送到电路部件的控制端。 利用可切换电阻网络，第一电阻或第二电阻连接在电路部件的输出端和集成电路的输出端之间，以在电路部件的输入侧和输出端之间产生电压降。 集成电路使得可以以取决于控制信号的方式在电路部件的输出端产生电流以及在电路部件的输入侧和输出端子之间落下的电压。 集成电路的晶体管的特性曲线族由集成电路确定。

公开(公告)号：US07051253B2

公开(公告)日：2006-05-23

申请号：US09931125

申请日：2001-08-16

申请人： Randall Rooney ,  Joerg Vollrath

发明人： Randall Rooney ,  Joerg Vollrath

IPC分类号： G11C29/00

CPC分类号： G11C29/10

摘要： According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.