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公开(公告)号：US20090109754A1
公开(公告)日：2009-04-30
申请号：US11928086
申请日：2007-10-30
申请人： Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue Ching Hui
发明人： Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue Ching Hui
CPC分类号： G11C16/3418 , Y10T29/49002
摘要： In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines.
摘要翻译： 在一个实施例中，非易失性存储器阵列，其中与分离的串中的最小特征尺寸宽度F一样小的窄字线从非易失性存储器阵列向外延伸并由更宽的连接器段连接。 加入的词语提供了新的机会。 首先，可以形成为覆盖字线的金属带可以通过金属连接器部分连接到字线。 连接器部分可以用作多晶硅字线和金属带之间的接口。 相同字符串中的两个相邻字线使用这些段共享单个金属带，从而减少阵列中的段和触点的总数。 在不同的串中连接字线的多晶硅接合段的增加的宽度提供了将连接扩大超出最小特征尺寸的机会，使得可以容易地在金属带和多晶硅字线之间进行接触。 第二，连接的字线需要更少的行解码器电路。 为每个连接的字线组提供一行解码器。
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公开(公告)号：US07684245B2
公开(公告)日：2010-03-23
申请号：US11928086
申请日：2007-10-30
申请人： Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue-Ching Hui
发明人： Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue-Ching Hui
CPC分类号： G11C16/3418 , Y10T29/49002
摘要： In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines.
摘要翻译： 在一个实施例中，非易失性存储器阵列，其中与分离的串中的最小特征尺寸宽度F一样小的窄字线从非易失性存储器阵列向外延伸并由更宽的连接器段连接。 加入的词语提供了新的机会。 首先，可以形成为覆盖字线的金属带可以通过金属连接器部分连接到字线。 连接器部分可以用作多晶硅字线和金属带之间的接口。 相同字符串中的两个相邻字线使用这些段共享单个金属带，从而减少阵列中的段和触点的总数。 在不同的串中连接字线的多晶硅接合段的增加的宽度提供了将连接扩大超出最小特征尺寸的机会，使得可以容易地在金属带和多晶硅字线之间进行接触。 第二，连接的字线需要更少的行解码器电路。 为每个连接的字线组提供一行解码器。
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3.发明授权公开(公告)号：US07158415B2
公开(公告)日：2007-01-02
申请号：US11089268
申请日：2005-03-24
IPC分类号： G11C16/10
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译： 使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。 外部测试装置将至少一个参考单元编程为预定值。 嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。
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4.发明申请公开(公告)号：US20060140030A1
公开(公告)日：2006-06-29
申请号：US11089268
申请日：2005-03-24
IPC分类号： G11C29/00
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译： 使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。 外部测试装置将至少一个参考单元编程为预定值。 嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。
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5.发明申请公开(公告)号：US20080232169A1
公开(公告)日：2008-09-25
申请号：US11688740
申请日：2007-03-20
IPC分类号： G11C11/34
摘要： A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bit lines. A plurality of sub arrays in each array each include a plurality of NAND flash memory cells coupled to local word lines and local bit lines. A local word line driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local word lines in its sub array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bit line driver is coupled between selected ones of the local bit lines in each sub array and selected ones of the plurality of bit lines.
摘要翻译： 闪存集成电路包括多个闪存阵列。 全局字线驱动器与每个阵列相关联，每个全局字线驱动器耦合到多个选择线。 多个读出放大器分别耦合到多个位线。 每个阵列中的多个子阵列每个包括耦合到本地字线和局部位线的多个NAND快闪存储器单元。 本地字线驱动器与每个子阵列相关联并且耦合到多个选择线，并且被配置为驱动其子阵列中的与本发明的子阵列中的多个NAND快闪存储器单元中的选定的一个相关联的本地字线中的一个， 数组。 局部位线驱动器耦合在每个子阵列中的局部位线中的选定的位线和多个位线中的选定的位线之间。
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6.发明申请公开(公告)号：US20050073355A1
公开(公告)日：2005-04-07
申请号：US10753273
申请日：2004-01-07
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译： 一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。 第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。 第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。 可变电阻用于设置电压输出的稳定电平。 通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。
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7.发明授权公开(公告)号：US07049880B2
公开(公告)日：2006-05-23
申请号：US11119675
申请日：2005-05-02
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译： 一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。 第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。 第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。 可变电阻用于设置电压输出的稳定电平。 通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。
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8.发明申请Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权具有阶段的感应放大器，以减少电流镜像负载中的电容失配公开(公告)号：US20080170454A1
公开(公告)日：2008-07-17
申请号：US11652770
申请日：2007-01-12
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译： 一种用于读取存储器单元状态的读出放大器电路。 在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。 耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上 不受由第一和第二级的瞬态特性提供的电容电流分量的影响。
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公开(公告)号：US20080164948A1
公开(公告)日：2008-07-10
申请号：US11619729
申请日：2007-01-04
IPC分类号： H03F3/04
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译： 电流镜电路包括耦合到第二电流镜晶体管的第一电流镜晶体管。 负载耦合到第二电流镜晶体管。 第一电流源耦合到第一电流镜晶体管以引起偏置电流流过第一电流镜晶体管，并且第二电流源耦合到第二电流镜晶体管并且与负载并联以分流 偏置电流远离负载。
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公开(公告)号：US20050189983A1
公开(公告)日：2005-09-01
申请号：US11119675
申请日：2005-05-02
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
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