-
1.发明授权公开(公告)号：US06426297B1
公开(公告)日：2002-07-30
申请号：US09905296
申请日：2001-07-13
IPC分类号： H01L21382
CPC分类号： H01L21/7684 , B24B37/042 , B24B49/16 , H01L21/3212
摘要： A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor wafer and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and a conductor core is deposited to fill the channel opening over the barrier layer. The semiconductor wafer is then subjected to chemical-mechanical polishing using a differential pressure between the center of the semiconductor wafer and its periphery.
摘要翻译： 提供了一种用于制造具有半导体器件的半导体衬底的集成电路的方法。 在半导体晶片上形成电介质层，并在电介质层中形成开口。 沉积阻挡层以对开口进行排列，并且沉积导体芯以填充阻挡层上的通道开口。 然后使用半导体晶片的中心与其周边之间的压差对半导体晶片进行化学机械抛光。
-
公开(公告)号：US20100261071A1
公开(公告)日：2010-10-14
申请号：US12759404
申请日：2010-04-13
CPC分类号： H01M4/66 , H01M4/133 , H01M4/366 , H01M4/587 , H01M4/626 , H01M4/661 , H01M4/667 , H01M10/0525 , Y10T29/49115
摘要： A cost effective method and apparatus are provided for forming metallized fibers and depositing multilayer films thereon to form thin film electrochemical energy storage devices. In one embodiment, a fibrous substrate is formed using a fiber spinning process and the fibrous substrate is plated with a copper layer using wet deposition. Multiple material layers are then deposited onto the copper layer to form a lithium-ion battery fiber.
摘要翻译： 提供了一种成本有效的方法和装置，用于形成金属化纤维并在其上沉积多层膜以形成薄膜电化学能量存储装置。 在一个实施例中，使用纤维纺丝工艺形成纤维基材，并且使用湿沉积将纤维基材镀铜层。 然后将多个材料层沉积到铜层上以形成锂离子电池纤维。
-
3.发明授权Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect 有权使用三元铜合金获得低电阻和大晶粒尺寸互连的方法公开(公告)号：US07696092B2
公开(公告)日：2010-04-13
申请号：US09994395
申请日：2001-11-26
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/2885 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.
摘要翻译： 一种制造集成电路的方法包括沿着横向侧壁和通孔孔的底部形成阻挡层，并且在通孔中通过材料提供三元铜合金以形成通孔。 通孔被配置成通过材料接收三元铜合金并电连接第一导电层和第二导电层。 三元铜合金通孔材料有助于通孔具有较低的电阻和增加的晶粒尺寸与人工晶界。
-
公开(公告)号：US07015504B2
公开(公告)日：2006-03-21
申请号：US10699903
申请日：2003-11-03
申请人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
发明人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
摘要翻译： 公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。 这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。 侧壁存储单元可以具有作为第一电极的晶片的位线，并且与第二形成的电极一起操作以激活在其间形成的有机物的一部分。
-
5.发明授权公开(公告)号：US06770905B1
公开(公告)日：2004-08-03
申请号：US10314054
申请日：2002-12-05
IPC分类号： H01L2940
CPC分类号： H01L51/0037 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0043 , H01L51/0046 , H01L51/0048 , H01L51/0052 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semiconductor layer and CuX layer made by implantation of a Group VIB element.
摘要翻译： 公开了一种具有通过注入制造的CuX层的有机存储单元。 有机存储单元由两个电极组成，至少一个电极含有铜，两个电极之间具有可控导电介质。 可控导电介质包含通过注入VIB族元素制成的有机半导体层和CuX层。
-
公开(公告)号：US06589408B1
公开(公告)日：2003-07-08
申请号：US10107778
申请日：2002-03-27
IPC分类号： C23C1435
CPC分类号： C23C14/3414 , C23C14/3407
摘要： A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a first alloy concentration and a side annular section having a second alloy concentration. The side annular section has ends coupled to ends of the top planar section. The first alloy concentration and the second alloy concentration are different.
摘要翻译： 非平面靶可以被配置用于等离子体气相沉积（PVD）工艺，其中离子轰击非平面靶，并使存在于非平面靶中的合金原子被敲击松动并形成合金膜层。 目标包括具有第一合金浓度的顶部平面部分和具有第二合金浓度的侧部环形部分。 侧面环形部分具有端部连接到顶部平面部分的端部。 第一合金浓度和第二合金浓度不同。
-
公开(公告)号：US06583051B2
公开(公告)日：2003-06-24
申请号：US09989972
申请日：2001-11-20
申请人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
发明人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.
-
公开(公告)号：US06346472B1
公开(公告)日：2002-02-12
申请号：US09784022
申请日：2001-02-16
IPC分类号： H01L214763
CPC分类号： H01L24/48 , H01L21/288 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L23/53242 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05017 , H01L2224/05018 , H01L2224/05019 , H01L2224/05546 , H01L2224/05557 , H01L2224/05559 , H01L2224/05571 , H01L2224/05664 , H01L2224/13099 , H01L2224/45124 , H01L2224/48463 , H01L2224/48764 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor metalization barrier, and manufacturing method therefor, is provided which is deposited from an aqueous solution containing the Period 4 transition metals of chromium, nickel, and copper deposited on a palladium-activated copper bonding pad.
摘要翻译： 提供一种半导体金属化屏障及其制造方法，其由含有沉积在钯活化铜键合垫上的铬，镍和铜的周期4过渡金属的水溶液沉积。
-
9.发明授权公开(公告)号：US06340633B1
公开(公告)日：2002-01-22
申请号：US09276839
申请日：1999-03-26
IPC分类号： H01L214763
CPC分类号： H01L21/76877 , H01L21/2885 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to deposit a large grain conductive layer in the channel.
摘要翻译： 提供了一种通过使用用于电镀工艺的斜坡电流密度在半导体通道和通孔中形成导电层的方法。 最初使用较低密度电流在通孔中沉积细晶粒导电层，然后使用较高密度在沟道中沉积大颗粒导电层。
-
10.发明授权Time ramped method for plating of high aspect ratio semiconductor vias and channels 有权用于电镀高纵横比半导体通孔和通道的时间渐变方法公开(公告)号：US06297157B1
公开(公告)日：2001-10-02
申请号：US09431516
申请日：1999-11-01
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , C25D5/18 , C25D7/123 , H01L21/76877
摘要： A method is provided for forming conductive layers in semiconductor vias by using forward and reverse pulses during the electroplating process which have time intervals between pulses which increase with time and for forming conductive layers in semiconductor channels by using forward pulses during the electroplating process which have time intervals between pulses which also increase with time. This allows fast deposition while reducing the deposition stress to eliminate voids and speeds up the overall manufacturing process.
摘要翻译： 提供了一种用于在电镀工艺期间通过使用正向和反向脉冲在电镀过程中形成导电层的方法，其间具有随时间增加的脉冲之间的时间间隔，并且通过在电镀工艺期间使用正向脉冲来形成半导体通道中的导电层， 脉冲之间的间隔也随时间增加。 这允许快速沉积，同时减少沉积应力以消除空隙并加速整个制造过程。
-
-
-
-
-
-
-
-
-
搜索结果
79 条记录 (耗时 0.024 秒)
