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公开(公告)号：US07645478B2
公开(公告)日：2010-01-12
申请号：US11094928
申请日：2005-03-31
申请人： Steven D. Thelss , Paul F. Baude , Michael A. Haase , Eric W. Hemmesch , Yaoqi J. Liu , Sergey S. Lamansky
发明人： Steven D. Thelss , Paul F. Baude , Michael A. Haase , Eric W. Hemmesch , Yaoqi J. Liu , Sergey S. Lamansky
CPC分类号： H01L51/0013 , H01L27/3244 , H01L29/7869 , H01L2251/5315 , Y10S428/917
摘要： Methods of forming displays are described. The displays have zinc oxide row and column drivers integrated onto the same display substrate as zinc oxide pixel transistors and organic light emitting diodes. The organic light emitting diodes are prepared, at least in part, using a thermal transfer process from a donor sheet.
摘要翻译： 描述形成显示器的方法。 显示器与氧化锌列和列驱动器集成在与氧化锌像素晶体管和有机发光二极管相同的显示基板上。 有机发光二极管至少部分地使用来自供体薄片的热转印工艺制备。
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2.发明授权Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes 有权使用集成的氧化锌行和列驱动器结合有机发光二极管的方法和显示公开(公告)号：US07298084B2
公开(公告)日：2007-11-20
申请号：US10979067
申请日：2004-11-02
CPC分类号： H01L27/1225 , H01L27/1214 , H01L27/1218 , H01L27/3244 , H01L27/3248 , H01L27/3262 , H01L29/7869 , H01L2251/5315 , H01L2251/5338
摘要： Methods and displays utilize row and column drivers with ZnO channels that control pixel transistors with ZnO channels, which in turn address OLEDs of an array to produce images of a display screen. A display backplane including the ZnO row and column drivers and the OLEDs may be constructed by utilizing aperture masking or a combination of photolithography and aperture masking. Monolithic integration of the ZnO row and column drivers together with the ZnO pixel transistors is thereby achieved.
摘要翻译： 方法和显示器利用具有ZnO通道的行和列驱动器来控制具有ZnO通道的像素晶体管，其又寻址阵列的OLED以产生显示屏的图像。 可以通过利用孔径掩模或光刻和孔径掩模的组合来构造包括ZnO行和列驱动器和OLED的显示器背板。 由此实现ZnO行和列驱动器与ZnO像素晶体管的整体集成。
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公开(公告)号：US07615501B2
公开(公告)日：2009-11-10
申请号：US11201587
申请日：2005-08-11
IPC分类号： H01L21/31
CPC分类号： C23C14/12 , B05D1/32 , B05D1/60 , C23C14/042 , H01L51/0021 , H01L51/0023 , H01L51/56
摘要： A method of making a patterned layer comprises directing a beam of vaporized material toward a reflector such that the beam of vaporized material impinges an impingement surface of the reflector and is redirected from the reflector through one or more apertures in a shadow mask and onto a deposition substrate to form a patterned material layer.
摘要翻译： 制造图案层的方法包括将蒸发的材料束引向反射器，使得气化材料束撞击反射器的冲击表面，并且通过荫罩中的一个或多个孔重新定向到反射器并且到达沉积物 衬底以形成图案化材料层。
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公开(公告)号：US07245151B2
公开(公告)日：2007-07-17
申请号：US11424450
申请日：2006-06-15
CPC分类号： G06K19/0713 , G06K19/0723 , H02M7/06 , H02M7/217
摘要： Logic circuitry is powered by a partially rectified alternating current (ac) waveform. The waveform is partially rectified in the sense that it does not provide a clean, primarily dc power signal. Instead, it is possible to power logic circuitry with a waveform that includes a substantial ac component. The partially rectified ac waveform may be applied to logic circuitry incorporating thin film transistors based on amorphous or polycrystalline organic semiconductors, inorganic semiconductors or combinations of both.
摘要翻译： 逻辑电路由部分整流的交流（ac）波形供电。 在不提供干净的主要直流电源信号的意义上，波形是部分整流的。 相反，可以用包含大量交流分量的波形为逻辑电路供电。 部分整流的交流波形可以应用于结合基于无定形或多晶有机半导体，无机半导体或两者的组合的薄膜晶体管的逻辑电路。
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公开(公告)号：US06821348B2
公开(公告)日：2004-11-23
申请号：US10076005
申请日：2002-02-14
申请人： Paul F. Baude , Patrick R. Fleming , Michael A. Haase , Tommie W. Kelley , Dawn V. Muyres , Steven Theiss
发明人： Paul F. Baude , Patrick R. Fleming , Michael A. Haase , Tommie W. Kelley , Dawn V. Muyres , Steven Theiss
IPC分类号： C23C1600
CPC分类号： C23C14/12 , C23C14/042 , C23C14/562 , G03F7/12 , H01L51/0004 , H01L51/0545 , H05K1/0393 , H05K3/143 , H05K2203/0271 , H05K2203/1545
摘要： In one embodiment, the invention is directed to aperture mask deposition techniques using aperture mask patterns formed in one or more elongated webs of flexible film. The techniques involve sequentially depositing material through mask patterns formed in the film to define layers, or portions of layers, of the circuit. A deposition substrate can also be formed from an elongated web, and the deposition substrate web can be fed through a series of deposition stations. Each deposition station may have an elongated web formed with aperture mask patterns. The elongated web of mask patterns feeds in a direction perpendicular to the deposition substrate web. In this manner, the circuit creation process can be performed in-line. Moreover, the process can be automated to reduce human error and increase throughput.
摘要翻译： 在一个实施例中，本发明涉及使用在一个或多个细长的柔性膜网中形成的孔掩模图案的孔掩模沉积技术。 这些技术涉及通过在膜中形成的掩模图案顺序沉积材料以限定电路的层或层的一部分。 沉积衬底也可以由细长的腹板形成，并且沉积衬底腹板可以通过一系列沉积站进给。 每个沉积站可以具有形成有孔掩模图案的细长腹板。 细长的掩模图形网沿垂直于沉积衬底腹板的方向进给。 以这种方式，可以在线执行电路创建处理。 此外，该过程可以自动化以减少人为错误并增加吞吐量。
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公开(公告)号：US06667215B2
公开(公告)日：2003-12-23
申请号：US10137562
申请日：2002-05-02
IPC分类号： H01L21336
CPC分类号： H01L51/0021 , B82Y10/00 , C23C14/042 , H01L21/31691 , H01L29/66742 , H01L51/001 , H01L51/0013 , H01L51/0016 , H01L51/0036 , H01L51/0037 , H01L51/0046 , H01L51/0052 , H01L51/0078 , H01L51/0545 , Y10S438/943 , Y10S438/944
摘要： A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.
摘要翻译： 一种用于制造晶体管的方法包括通过固定荫罩中的单个孔将源电极和漏极特征沉积到衬底上，所述孔具有至少两个相对的边缘; 其中特征的形状由源材料相对于基底的孔径和位置限定。
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公开(公告)号：US5963573A
公开(公告)日：1999-10-05
申请号：US920179
申请日：1997-08-25
申请人： Michael A. Haase , Paul F. Baude
发明人： Michael A. Haase , Paul F. Baude
CPC分类号： H01L33/28 , H01S5/10 , H01S5/327 , H01S5/0021 , H01S5/0655 , H01S5/2219 , H01S5/2231
摘要： A II-VI semiconductor light emitting device includes a II-VI semiconductor light emitting region and a II-VI semiconductor waveguide layer. A light absorbing layer is provided near the II-VI semiconductor waveguide layer, outside of the active region. The light absorbing layer absorbs extraneous radiation thereby reducing dark line defects (DLDs).
摘要翻译： II-VI族半导体发光器件包括II-VI半导体发光区域和II-VI半导体波导层。 在活性区域外部，在II-VI半导体波导层附近设置光吸收层。 光吸收层吸收外来辐射，从而减少暗线缺陷（DLD）。
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公开(公告)号：US07297361B2
公开(公告)日：2007-11-20
申请号：US10940448
申请日：2004-09-14
申请人： Paul F. Baude , Patrick R. Fleming , Michael A. Haase , Tommie W. Kelley , Dawn V. Muyres , Steven Theiss
发明人： Paul F. Baude , Patrick R. Fleming , Michael A. Haase , Tommie W. Kelley , Dawn V. Muyres , Steven Theiss
CPC分类号： C23C14/12 , C23C14/042 , C23C14/562 , G03F7/12 , H01L51/0004 , H01L51/0545 , H05K1/0393 , H05K3/143 , H05K2203/0271 , H05K2203/1545
摘要： A method for circuit fabrication includes positioning first and second webs of film in proximity to each other, wherein the second web of film defines a deposition mask, and deposition material on the first web of film through the deposition mask pattern defined by the second web of the to create at least a portion of an integrated circuit.
摘要翻译： 一种用于电路制造的方法包括将第一和第二薄膜网彼此靠近地定位，其中第二薄膜网限定了沉积掩模，并且通过由第二网片 电影以创建至少一部分集成电路。
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公开(公告)号：US07241688B2
公开(公告)日：2007-07-10
申请号：US11118811
申请日：2005-04-29
申请人： Paul F. Baude , Patrick R. Fleming , Michael A. Haase , Tommie W. Kelley , Dawn V. Muyres , Steven Theiss
发明人： Paul F. Baude , Patrick R. Fleming , Michael A. Haase , Tommie W. Kelley , Dawn V. Muyres , Steven Theiss
IPC分类号： H01L21/44
CPC分类号： H01L51/0011 , C23C14/042 , C23C14/562 , G03F7/12 , H01L51/0081 , H01L51/0087 , Y10S438/942 , Y10S438/943
摘要： Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circuit elements for electronic displays and low-cost integrated circuits such as radio frequency identification (RFID) circuits. In addition, the techniques can be advantageous in the fabrication of integrated circuits incorporating organic semiconductors, which typically are not compatible with wet processes.
摘要翻译： 描述了使用孔径掩模的孔径掩模和沉积技术。 此外，描述了用于创建孔径掩模和用于使用孔径掩模的其它技术的技术。 各种技术在产生用于电子显示器的电路元件和诸如射频识别（RFID）电路的低成本集成电路中尤其有用。 此外，这些技术在加入有机半导体的集成电路的制造中是有利的，其通常与湿法不兼容。
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公开(公告)号：US07078937B2
公开(公告)日：2006-07-18
申请号：US10738082
申请日：2003-12-17
CPC分类号： G06K19/0713 , G06K19/0723 , H02M7/06 , H02M7/217
摘要： Logic circuitry is powered by a partially rectified alternating current (ac) waveform. The waveform is partially rectified in the sense that it does not provide a clean, primarily dc power signal. Instead, it is possible to power logic circuitry with a waveform that includes a substantial ac component. The partially rectified ac waveform may be applied to logic circuitry incorporating thin film transistors based on amorphous or polycrystalline organic semiconductors, inorganic semiconductors or combinations of both.
摘要翻译： 逻辑电路由部分整流的交流（ac）波形供电。 在不提供干净的主要直流电源信号的意义上，波形是部分整流的。 相反，可以用包含大量交流分量的波形为逻辑电路供电。 部分整流的交流波形可以应用于结合基于无定形或多晶有机半导体，无机半导体或两者的组合的薄膜晶体管的逻辑电路。
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