公开(公告)号：US20080059278A1

公开(公告)日：2008-03-06

申请号：US11565677

申请日：2006-12-01

申请人： Steven Medina ,  Joseph Cox ,  Kenneth Marr

发明人： Steven Medina ,  Joseph Cox ,  Kenneth Marr

IPC分类号： G06F9/46

CPC分类号： G06Q10/06 ,  G06Q10/063112 ,  G06Q10/063116

摘要： A system, method, and computer readable medium for offering uptime adjustments to a work schedule for at least one currently unscheduled agent possessing at least one skill type, that comprises, accepting at least one forecasted manpower requirement of zero or more agents for an interval of time for a skill, requesting an uptime display for an unscheduled time period of the at least one currently unscheduled agent, assessing the type and number of skill types of the at least one currently unscheduled agent, determining a manpower availability for the an interval of time based upon all agents currently scheduled for each skill type based upon the forecasted manpower requirement, calculating a manpower delta between the forecasted manpower requirement for the an interval of time and the determined manpower availability for each skill type, and offering an uptime adjustment if the calculated manpower delta shows additional manpower is required for any skill possessed by the at least one currently unscheduled agent.

摘要翻译： 一种系统，方法和计算机可读介质，用于为具有至少一种技能类型的至少一个当前非调度代理提供对工作进度的正常运行时间调整，其包括：接收零个或多个代理的至少一个预测人力需求， 技能的时间，请求对至少一个当前非调度代理的非预定时间段的正常运行时间显示，评估至少一个当前非调度代理的技能类型的类型和数量，确定一段时间的人力可用性 基于目前根据预测的人力需求计划的每个技能类型的所有代理人，计算一段时间内预测的人力需求与确定的每种技能类型的人力可用性之间的人力三角洲，并且如果计算出的 人力三角洲显示至少一个c拥有的任何技能需要额外的人力 非常不定期的代理

公开(公告)号：US20070019480A1

公开(公告)日：2007-01-25

申请号：US11185079

申请日：2005-07-20

申请人： Dustin Conner ,  Mark Hutchinson ,  Scott Gatzemeier ,  Kenneth Marr ,  Jason Andrus ,  Colby Hansen ,  Theodore Pekny ,  Tyson Stichka

发明人： Dustin Conner ,  Mark Hutchinson ,  Scott Gatzemeier ,  Kenneth Marr ,  Jason Andrus ,  Colby Hansen ,  Theodore Pekny ,  Tyson Stichka

IPC分类号： G11C7/06 ,  G11C7/02

CPC分类号： G11C29/50 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/5006

摘要： A memory device compares, within the memory device, a signal indicative of a current drawn by one or more select lines to a reference signal, and indicates whether the signal indicative of the current drawn by the one or more select lines exceeds the reference signal.

摘要翻译： 存储器装置在存储器装置内比较指示由一个或多个选择线对参考信号汲取的电流的信号，并且指示指示由一个或多个选择线汲取的电流的信号是否超过参考信号。

公开(公告)号：US20050156618A1

公开(公告)日：2005-07-21

申请号：US11054667

申请日：2005-02-09

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G01R31/28 ,  G01R31/26 ,  G01R31/02

CPC分类号： G01R31/2855 ,  G01R31/2831 ,  G01R31/2863

摘要： A large-scale support carries semiconductor devices and at least one pair of common conductive regions in communication therewith. Each common conductive region is configured to be electrically connected with both a force contact and a sense contact of stress or test equipment. Such equipment includes at least one pair of force contacts for applying a force voltage across a pair of common conductive regions and, thus, across the support. A corresponding pair of sense contacts facilitates monitoring of a voltage applied across each of the semiconductor devices by the force contacts. Methods and systems for evaluating a voltage that has been applied to two or more semiconductor devices by way of a single pair of force contacts are also disclosed, as are methods and systems for, in response to a measured voltage, modifying the force voltage so that a desired voltage may be applied across each of the semiconductor devices.

摘要翻译： 大规模的支撑件承载半导体器件和与其通信的至少一对公共导电区域。 每个公共导电区域构造成与应力或测试设备的力接触和感测接触两者电连接。 这种设备包括至少一对力接触件，用于在一对公共导电区域上施加力电压，并因此施加跨过支撑件的力电压。 相应的一对感测触点便于通过力触点监测施加在每个半导体器件上的电压。 还公开了通过单个力接触来评估已经施加到两个或更多个半导体器件的电压的方法和系统，响应于测量的电压，修改电压使得使得 可以在每个半导体器件上施加期望的电压。

公开(公告)号：US20050174138A1

公开(公告)日：2005-08-11

申请号：US11065016

申请日：2005-02-24

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44

CPC分类号： G01R31/2856 ,  G01R31/287 ,  G01R31/318505 ,  G01R31/318511 ,  G11C16/04 ,  G11C29/006 ,  G11C29/12 ,  G11C29/44 ,  G11C2029/4402 ,  G11C2029/5002

摘要： A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. Circuits and systems associated with the method of the present invention are also disclosed.

摘要翻译： 公开了一种用于从晶片级老化确定老化可靠性的方法，电路和系统。 根据本发明的方法包括在晶片级老化测试的持续时间内的时间点上将每个IC管芯中的故障数记录在片上的非易失性元件中。 每个IC芯片中的故障数量及其相关联的时间点可用于创建老化可靠性曲线，其通常使用其他可能具有较低成本效益或不可能通过未封装的IC芯片实现的其他过程得到。 还公开了与本发明的方法相关的电路和系统。

公开(公告)号：US20050018499A1

公开(公告)日：2005-01-27

申请号：US10925543

申请日：2004-08-24

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44

CPC分类号： G01R31/2856 ,  G01R31/287 ,  G01R31/318505 ,  G01R31/318511 ,  G11C16/04 ,  G11C29/006 ,  G11C29/12 ,  G11C29/44 ,  G11C2029/4402 ,  G11C2029/5002

摘要： An apparatus for determining burn-in reliability from wafer level burn-in is disclosed. The apparatus according td the present invention includes nonvolatile elements on an integrated circuit for recording the number of failures at various points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. A memory device associated with the method of the present invention is also disclosed.

摘要翻译： 公开了一种用于从晶片级老化确定老化可靠性的装置。 根据本发明的装置包括用于在晶片级老化测试的持续时间内记录不同时间点的故障次数的集成电路上的非易失性元件。 每个IC芯片中的故障数量及其相关联的时间点可用于创建老化可靠性曲线，其通常使用其他可能具有较低成本效益或不可能通过未封装的IC芯片实现的其他过程得到。 还公开了与本发明的方法相关联的存储器件。

公开(公告)号：US20050015654A1

公开(公告)日：2005-01-20

申请号：US10609312

申请日：2003-06-24

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G11C29/00 ,  H02H3/05

CPC分类号： G11C29/832 ,  G11C29/83

摘要： A memory device has a number of memory segments connected to a supply source through a supply control circuit. If one of the memory segments is defective, the supply control circuit isolates the defective memory segment from the supply source. The memory device replaces the defective memory segment with a redundant segment.

摘要翻译： 存储器件具有通过电源控制电路连接到电源的多个存储器段。 如果其中一个存储器段有故障，则电源控制电路将有缺陷的存储器段与供电源隔离。 存储器件用冗余段替换有缺陷的存储器段。

公开(公告)号：US20070190751A1

公开(公告)日：2007-08-16

申请号：US11725296

申请日：2007-03-19

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： H01L21/326 ,  H01L21/82 ,  H01L29/00

CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： A fuse for use in semiconductor devices, semiconductor devices including the fuse, methods of fabricating the fuse, and methods of using the fuse. The fuse includes terminals and a programmable region between the terminals. The programmable region may have less mass than the terminals. The programmable region may include metal silicide, which is rendered discontinuous by agglomeration or melting when a programming current is applied to one of the terminals. Construction of the fuse or features over the fuse may prevent programming of the fuse with a laser.

摘要翻译： 用于半导体器件的保险丝，包括保险丝的半导体器件，制造保险丝的方法以及使用保险丝的方法。 保险丝包括端子和端子之间的可编程区域。 可编程区域的质量可能比端子少。 可编程区域可以包括金属硅化物，当编程电流施加到端子之一时，其通过聚集或熔化而变得不连续。 保险丝或特征超过保险丝的构造可能会导致使用激光对熔丝进行编程。

公开(公告)号：US20060231922A1

公开(公告)日：2006-10-19

申请号：US11426523

申请日：2006-06-26

申请人： Kenneth Marr ,  John Porter

发明人： Kenneth Marr ,  John Porter

IPC分类号： H01L29/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0248 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.

摘要翻译： 根据本发明的实施例，电路具有用于保护栅介质反熔丝电路中的高压晶体管的元件。 反熔丝在耦合以接收升高电压的第一端子和第二端子之间具有栅极电介质层，并且高压晶体管耦合到反熔丝并具有栅极端子。 电源电压和升高电压之间的中间电压耦合到高电压晶体管的栅极端子，以保护高压晶体管。

公开(公告)号：US20050158919A1

公开(公告)日：2005-07-21

申请号：US11082066

申请日：2005-03-16

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link joining the spaced-apart terminals and including a single layer of conductive material. A first, lower layer of the terminals of each fuse may be formed from conductively doped polysilicon. The second, upper layer of each fuse terminal may be formed from a polycide, a metal silicide, a metal, or a conductive alloy. The conductive link of each fuse may be formed from either the material of the first layer or the material of the second layer. Methods for fabricating the fuse include forming the first and second layers and patterning the first and second layers so as to form a fuse with the desired structure.

摘要翻译： 用于半导体器件的熔断器包括具有至少两层导电材料的间隔开的端子和连接间隔开的端子并包括单层导电材料的单层导电连接。 每个保险丝的端子的第一个下层可以由导电掺杂的多晶硅形成。 每个熔丝端子的第二上层可以由多晶硅，金属硅化物，金属或导电合金形成。 每个保险丝的导电连接可由第一层的材料或第二层的材料形成。 用于制造熔丝的方法包括形成第一层和第二层并且图案化第一层和第二层以便形成具有所需结构的熔丝。

公开(公告)号：US20050029598A1

公开(公告)日：2005-02-10

申请号：US10931366

申请日：2004-08-31

申请人： Kenneth Marr ,  John Porter

发明人： Kenneth Marr ,  John Porter

IPC分类号： G11C17/18 ,  H01L23/525 ,  H01L29/78 ,  H01L29/04

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0248 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.