公开(公告)号：US20130320411A1

公开(公告)日：2013-12-05

申请号：US13488581

申请日：2012-06-05

申请人： Su-Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Su-Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545

摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.

公开(公告)号：US08383490B2

公开(公告)日：2013-02-26

申请号：US13191540

申请日：2011-07-27

申请人： Su Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak

发明人： Su Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak

IPC分类号： H01L21/76

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/78609

摘要： After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

公开(公告)号：US20130026570A1

公开(公告)日：2013-01-31

申请号：US13191540

申请日：2011-07-27

申请人： Su Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak

发明人： Su Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak

IPC分类号： H01L29/772 ,  H01L23/48 ,  H01L21/28

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/78609

摘要： After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

公开(公告)号：US20110081765A1

公开(公告)日：2011-04-07

申请号：US12571483

申请日：2009-10-01

申请人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

公开(公告)号：US08629008B2

公开(公告)日：2014-01-14

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/02

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US20130175622A1

公开(公告)日：2013-07-11

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US08623730B2

公开(公告)日：2014-01-07

申请号：US13617866

申请日：2012-09-14

申请人： Susan S. Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III

发明人： Susan S. Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/336

CPC分类号： H01L29/42384 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78651 ,  H01L29/78654

摘要： A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

摘要翻译： 提供了一种用于制造晶体管的方法。 在半导体层上形成替代栅极叠层，形成栅极间隔物，形成电介质层。 去除虚拟栅极堆叠以形成空腔。 在空腔中形成栅极电介质和功函数金属层。 空腔填充有栅极导体。 门导体和功函数金属层中的仅一个选择性地凹入。 在凹部中形成氧化膜，使得其上表面与电介质层的上表面共面。 氧化膜用于选择性地生长氧化物盖。 形成并蚀刻层间电介质以形成用于源/漏接触的空腔。 源极/漏极接触形成在接触腔中，源极/漏极触点的一部分直接位于氧化物盖上。

公开(公告)号：US20120178236A1

公开(公告)日：2012-07-12

申请号：US13422138

申请日：2012-03-16

申请人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

公开(公告)号：US08853076B2

公开(公告)日：2014-10-07

申请号：US13607856

申请日：2012-09-10

申请人： Su Chen Fan ,  David V. Horak ,  Shom Ponoth ,  David L. Rath ,  Muthumanickam Sankarapandian

发明人： Su Chen Fan ,  David V. Horak ,  Shom Ponoth ,  David L. Rath ,  Muthumanickam Sankarapandian

IPC分类号： H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.

摘要翻译： 本文公开了金属栅极结构中的自对准触点和制造方法。 该方法包括形成具有侧壁结构的金属栅极结构。 该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。 该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。

公开(公告)号：US08772168B2

公开(公告)日：2014-07-08

申请号：US13353708

申请日：2012-01-19

申请人： Ruilong Xie ,  Balasubramanian Pranatharthi Haran ,  David V. Horak ,  Su Chen Fan

发明人： Ruilong Xie ,  Balasubramanian Pranatharthi Haran ,  David V. Horak ,  Su Chen Fan

IPC分类号： H01L21/311

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.

摘要翻译： 通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。 实施例包括在衬底上形成替代的栅极结构，所述替换的栅极结构包括具有空腔的ILD，在ILD的顶表面上的第一金属和衬里的空腔，以及在第一金属上填充空腔的第二金属， 平面化第一和第二金属，在第二金属上形成氧化物，去除氧化物，使空腔中的第一和第二金属凹陷，形成凹陷，并用电介质材料填充凹槽。 实施例还包括具有垂直侧壁，梯形形状，T形或Y形的电介质盖。