公开(公告)号：US06881620B1

公开(公告)日：2005-04-19

申请号：US10707357

申请日：2003-12-08

申请人： Su-Chen Lai ,  Chao-Hsi Chung

发明人： Su-Chen Lai ,  Chao-Hsi Chung

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/1087

摘要： A method of fabricating a deep trench capacitor is provided. A substrate with a deep trench thereon is provided. A bottom electrode is formed at a bottom of the deep trench and a capacitor dielectric layer, a first conductive layer, a protective layer and a collar layer are sequentially formed on the surface of the deep trench. The protective layer and the collar oxide layer on the surface of the first conductive layer are removed, material is deposited into the deep trench to form a material layer. A portion of the material layer is removed to form a first opening. Thereafter, collar oxide layer and the protective layer not covered by the material layer is removed. A portion of the mask layer and the protective layer on the sidewall of the first opening is removed to form a second opening. After removing the material layer, a second conductive layer and a third conductive layer are sequentially formed in the deep trench.

摘要翻译： 提供一种制造深沟槽电容器的方法。 提供其上具有深沟槽的衬底。 底部电极形成在深沟槽的底部，并且在深沟槽的表面上依次形成电容器电介质层，第一导电层，保护层和套环层。 去除第一导电层表面上的保护层和环氧化物层，将材料沉积到深沟槽中以形成材料层。 去除材料层的一部分以形成第一开口。 此后，去除环氧化物层和未被材料层覆盖的保护层。 去除掩模层的一部分和第一开口的侧壁上的保护层以形成第二开口。 在去除材料层之后，在深沟槽中顺序地形成第二导电层和第三导电层。

公开(公告)号：US07163858B2

公开(公告)日：2007-01-16

申请号：US10904479

申请日：2004-11-12

申请人： Chao-Hsi Chung

发明人： Chao-Hsi Chung

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： A method of fabrication deep trench capacitors includes forming a plurality of deep trenches in a substrate. A bottom electrode is formed in the substrate surrounding the bottom of each deep trench. A capacitor dielectric layer and a first conductive layer are formed at the bottom of each deep trench. A collar oxide layer is formed on the sidewall of the deep trench exposed by the first conductive layer. A second conductive layer fills each deep trench. An opening is formed in a region predetermined for an isolation structure between adjacent deep trenches, wherein the depth of the opening is greater than that of the isolation structure. An isolation layer is filled in the opening.

摘要翻译： 制造深沟槽电容器的方法包括在衬底中形成多个深沟槽。 底部电极形成在每个深沟槽的底部周围的基板中。 在每个深沟槽的底部形成电容器电介质层和第一导电层。 在由第一导电层暴露的深沟槽的侧壁上形成环状氧化物层。 第二导电层填充每个深沟槽。 在相邻深沟槽之间的隔离结构预定的区域中形成开口，其中开口的深度大于隔离结构的深度。 隔离层填充在开口中。

公开(公告)号：US08143136B2

公开(公告)日：2012-03-27

申请号：US12979775

申请日：2010-12-28

申请人： Chao-Hsi Chung

发明人： Chao-Hsi Chung

IPC分类号： H01L21/8242 ,  H01L29/41

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： A method for fabricating a crown-shaped capacitor includes providing a first dielectric layer with a protective pillar formed thereover, including a first conductive layer, a protective layer, and a mask layer. A second conductive layer is formed over a sidewall of the protective pillar. A first capacitance layer and a third conductive layer are formed over the first dielectric layer. A sacrificial layer is formed over the third conductive layer. The sacrificial layer, the third conductive layer, the first capacitance layer, the second conductive layer, and the mask layer above the protective layer are partially removed. The second conductive layer and the third conductive are removed to form a recess adjacent to the first capacitance layer. The protective layer is removed and an opening is formed to expose the first and second conductive layers. A second capacitance layer and a fourth conductive layer are formed in the opening. The sacrificial layer is removed to expose the third conductive layer.

摘要翻译： 一种用于制造冠状电容器的方法包括：提供具有形成在其上的保护柱的第一介电层，包括第一导电层，保护层和掩模层。 在保护柱的侧壁上形成第二导电层。 第一电容层和第三导电层形成在第一介电层上。 牺牲层形成在第三导电层上。 部分地去除了保护层上方的牺牲层，第三导电层，第一电容层，第二导电层和掩模层。 去除第二导电层和第三导体以形成与第一电容层相邻的凹部。 去除保护层并形成开口以暴露第一和第二导电层。 第二电容层和第四导电层形成在开口中。 去除牺牲层以暴露第三导电层。

公开(公告)号：US07354837B2

公开(公告)日：2008-04-08

申请号：US11217369

申请日：2005-09-02

申请人： Chao-Hsi Chung ,  Chu-Chun Hu ,  Chih-Cheng Wang

发明人： Chao-Hsi Chung ,  Chu-Chun Hu ,  Chih-Cheng Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

摘要： A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer in the array area are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.

摘要翻译： 提供了半导体器件的制造方法。 衬底具有带有第一栅极的阵列区域和具有第二栅极的周边区域。 依次形成由不同材料制成的第一和第二隔离层以覆盖第一栅极，第二栅极和衬底。 去除第二隔离层的一部分以在第一和第二栅极的侧壁上形成间隔物，并且在第一栅极的顶部，第二栅极的顶部和衬底的表面上暴露第一隔离层。 去除阵列区域中第一隔离层上的间隔物。 去除第一栅极的顶部上的第一隔离层和衬底的表面，从而使第一隔离层的一部分覆盖在第一栅极的侧壁上。

公开(公告)号：US20080032471A1

公开(公告)日：2008-02-07

申请号：US11580807

申请日：2006-10-13

申请人： Wen-Shuo Kuo ,  Chao-Hsi Chung ,  Yung Yao Lee ,  Hui-Min Li

发明人： Wen-Shuo Kuo ,  Chao-Hsi Chung ,  Yung Yao Lee ,  Hui-Min Li

IPC分类号： H01L21/8242

CPC分类号： H01L21/76224 ,  H01L27/1087

摘要： A method for manufacturing a shallow trench isolation structure in a deep trench and application thereof are provided, wherein the deep trench having an upper electrode and an insulation layer on the upper electrode is formed in a substrate which has a pad insulation layer. The method comprises the following steps: forming a hard mask on the first insulation layer, doping a first portion of the hard mask, removing the undoped portion of the hard mask to expose a portion of the first insulation layer and reserve the first portion of the hard mask, removing the exposed portion of the first insulation layer to expose a portion of the upper electrode, and forming a conductive layer on the exposed portion of the upper electrode wherein a predetermined distance exists between the upper surface of the conductive layer and the pad insulation layer.

摘要翻译： 提供一种在深沟槽中制造浅沟槽隔离结构的方法及其应用，其中在具有衬垫绝缘层的衬底中形成具有上电极和上电极上的绝缘层的深沟槽。 该方法包括以下步骤：在第一绝缘层上形成硬掩模，掺杂硬掩模的第一部分，去除硬掩模的未掺杂部分以暴露第一绝缘层的一部分并保留第一绝缘层的第一部分 去除所述第一绝缘层的暴露部分以暴露所述上电极的一部分，以及在所述上电极的暴露部分上形成导电层，其中在所述导电层的所述上表面和所述焊盘之间存在预定距离 绝缘层。

公开(公告)号：US20060220089A1

公开(公告)日：2006-10-05

申请号：US11445847

申请日：2006-06-02

申请人： Chao-Hsi Chung ,  Jung-Wu Chien

发明人： Chao-Hsi Chung ,  Jung-Wu Chien

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10867

摘要： A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.

公开(公告)号：US20060216889A1

公开(公告)日：2006-09-28

申请号：US11092150

申请日：2005-03-28

申请人： Chao-Hsi Chung ,  Jung-Wu Chien

发明人： Chao-Hsi Chung ,  Jung-Wu Chien

IPC分类号： H01L21/336

CPC分类号： H01L27/1087 ,  H01L27/10867

摘要： A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.

摘要翻译： 存储器电荷存储节点（120.1,120.2,120.3）至少部分地位于沟槽（124）中。 存储器包括晶体管，其包括存在于沟槽的第一侧（124.1）但不是第二侧（124.2）的源/漏区（170）。 在形成提供电荷存储节点的至少一部分的导电材料（120.3）之前，邻近第二侧（124.2）形成阻挡特征（704）以阻挡导电材料（120.3）。 阻挡特征可以是最终结构中的电介质，或者可以是在导电材料沉积之后去除以使电介质留下空间的牺牲特征。 可以使用包括多个直条的掩模（710）来对存储器阵列中的多个沟槽的阻挡特征进行图案化，每个直条在行方向上贯穿存储器阵列。 电荷存储节点在邻近源极/漏极区的沟槽的第一侧具有突起（120.3），并且还具有横向邻近突起的顶表面部分（T）。 沟槽侧壁在上表面部分（T）上方具有在第二侧（124.2）上的基本上直的部分（S）。 沟槽侧壁上的电介质（144.1,144.2,188）具有在第二侧比在沟槽的第一侧更厚的部分（188）。

公开(公告)号：US07348622B2

公开(公告)日：2008-03-25

申请号：US11445847

申请日：2006-06-02

申请人： Chao-Hsi Chung ,  Jung-Wu Chien

发明人： Chao-Hsi Chung ,  Jung-Wu Chien

IPC分类号： H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10867

摘要： A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.

摘要翻译： 存储器电荷存储节点（120.1,120.2,120.3）至少部分地位于沟槽（124）中。 存储器包括晶体管，其包括存在于沟槽的第一侧（124.1）但不是第二侧（124.2）的源/漏区（170）。 在形成提供电荷存储节点的至少一部分的导电材料（120.3）之前，邻近第二侧（124.2）形成阻挡特征（704）以阻挡导电材料（120.3）。 阻挡特征可以是最终结构中的电介质，或者可以是在导电材料沉积之后去除以使电介质留下空间的牺牲特征。 可以使用包括多个直条的掩模（710）来对存储器阵列中的多个沟槽的阻挡特征进行图案化，每个直条在行方向上贯穿存储器阵列。 电荷存储节点在邻近源极/漏极区的沟槽的第一侧具有突起（120.3），并且还具有横向邻近突起的顶表面部分（T）。 沟槽侧壁在上表面部分（T）上方具有在第二侧（124.2）上的基本上直的部分（S）。 沟槽侧壁上的电介质（144.1,144.2,188）具有在第二侧比在沟槽的第一侧更厚的部分（188）。

公开(公告)号：US07232719B2

公开(公告)日：2007-06-19

申请号：US11092150

申请日：2005-03-28

申请人： Chao-Hsi Chung ,  Jung-Wu Chien

发明人： Chao-Hsi Chung ,  Jung-Wu Chien

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L27/10867

摘要： A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.

摘要翻译： 存储器电荷存储节点（120.1,120.2,120.3）至少部分地位于沟槽（124）中。 存储器包括晶体管，其包括存在于沟槽的第一侧（124.1）但不是第二侧（124.2）的源/漏区（170）。 在形成提供电荷存储节点的至少一部分的导电材料（120.3）之前，邻近第二侧（124.2）形成阻挡特征（704）以阻挡导电材料（120.3）。 阻挡特征可以是最终结构中的电介质，或者可以是在导电材料沉积之后去除以使电介质留下空间的牺牲特征。 可以使用包括多个直条的掩模（710）来对存储器阵列中的多个沟槽的阻挡特征进行图案化，每个直条在行方向上贯穿存储器阵列。 电荷存储节点在邻近源极/漏极区的沟槽的第一侧具有突起（120.3），并且还具有横向邻近突起的顶表面部分（T）。 沟槽侧壁在上表面部分（T）上方具有在第二侧（124.2）上的基本上直的部分（S）。 沟槽侧壁上的电介质（144.1,144.2,188）具有在第二侧比在沟槽的第一侧更厚的部分（188）。

公开(公告)号：US20070015324A1

公开(公告)日：2007-01-18

申请号：US11217369

申请日：2005-09-02

申请人： Chao-Hsi Chung ,  Chu-Chun Hu ,  Chih-Cheng Wang

发明人： Chao-Hsi Chung ,  Chu-Chun Hu ,  Chih-Cheng Wang

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823468 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

摘要： A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer in the array area are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.

摘要翻译： 提供了半导体器件的制造方法。 衬底具有带有第一栅极的阵列区域和具有第二栅极的周边区域。 依次形成由不同材料制成的第一和第二隔离层以覆盖第一栅极，第二栅极和衬底。 去除第二隔离层的一部分以在第一和第二栅极的侧壁上形成间隔物，并且在第一栅极的顶部，第二栅极的顶部和衬底的表面上暴露第一隔离层。 去除阵列区域中第一隔离层上的间隔物。 去除第一栅极的顶部上的第一隔离层和衬底的表面，从而使第一隔离层的一部分覆盖在第一栅极的侧壁上。