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    Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods
    1.
    发明申请
    Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods 审中-公开
    包括侧壁电阻层的电阻随机存取存储器件及相关方法

    公开(公告)号：US20080247219A1

    公开(公告)日：2008-10-09

    申请号：US12062042

    申请日：2008-04-03

    申请人： Suk-Hun Choi ,  In-Gyu Baek ,  Seong-Kyu Yun ,  Jong-Heun Lim ,  Chagn-Ki Hong ,  Bo-Un Yoon

    发明人： Suk-Hun Choi ,  In-Gyu Baek ,  Seong-Kyu Yun ,  Jong-Heun Lim ,  Chagn-Ki Hong ,  Bo-Un Yoon

    IPC分类号： G11C11/00 ,  H01C17/00

    CPC分类号： H01L45/04 ,  H01C17/06533 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1666 ,  Y10T29/49082

    摘要： A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions of the first metal pattern may be between the substrate and the first insulating layer, and the first insulating layer may have a first opening therein exposing a portion of the first metal pattern. The electrode may be in the opening with the electrode being electrically coupled with the exposed portion of the first metal pattern. The first insulating layer may be between the second insulating layer and the substrate, and the second insulating layer may have a second opening therein exposing a portion of the electrode. The resistive memory layer may be on side faces of the second opening and on portions of the electrode, and the second metal pattern may be in the second opening with the resistive memory layer between the second metal pattern and the side faces of the second opening and between the second metal pattern and the electrode. Related methods are also discussed.

    摘要翻译： 电阻随机存取存储器（RRAM）器件可以包括衬底上的第一金属图案，第一金属图案上的第一绝缘层和衬底上的第一绝缘层，电极，第一绝缘层上的第二绝缘层，电阻存储层 ，和第二金属图案。 第一金属图案的部分可以在基板和第一绝缘层之间，并且第一绝缘层可以具有其中暴露第一金属图案的一部分的第一开口。 电极可以在开口中，其中电极与第一金属图案的暴露部分电耦合。 第一绝缘层可以在第二绝缘层和衬底之间，并且第二绝缘层可以具有暴露电极的一部分的第二开口。 电阻性存储层可以在第二开口的侧面和电极的部分上，并且第二金属图案可以在第二开口中，第二金属图案和第二开口的侧面之间的电阻性存储层， 在第二金属图案和电极之间。 还讨论了相关方法。

    Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics
    2.
    发明授权
    Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics 有权
    制造半导体器件的方法包括具有改进的缺陷密度和表面粗糙度特性的沟道层

    公开(公告)号：US07678625B2

    公开(公告)日：2010-03-16

    申请号：US11962742

    申请日：2007-12-21

    申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    IPC分类号： H01L21/84

    CPC分类号： H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

    摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

    摘要翻译： 制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。 单晶半导体层包括从其表面延伸的突起。 在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。 执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。 可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。 还讨论了制造叠层半导体存储器件的相关方法。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING CHANNEL LAYERS HAVING IMPROVED DEFECT DENSITY AND SURFACE ROUGHNESS CHARACTERISTICS
    4.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING CHANNEL LAYERS HAVING IMPROVED DEFECT DENSITY AND SURFACE ROUGHNESS CHARACTERISTICS 有权
    制备半导体器件的方法，包括具有改善的缺陷密度和表面粗糙特性的通道层

    公开(公告)号：US20080160726A1

    公开(公告)日：2008-07-03

    申请号：US11962742

    申请日：2007-12-21

    申请人： Jong Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    发明人： Jong Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

    摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

    摘要翻译： 制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。 单晶半导体层包括从其表面延伸的突起。 在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。 执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。 可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。 还讨论了制造叠层半导体存储器件的相关方法。

    METHODS OF RECYCLING A SUBSTRATE INCLUDING USING A CHEMICAL MECHANICAL POLISHING PROCESS
    5.
    发明申请
    METHODS OF RECYCLING A SUBSTRATE INCLUDING USING A CHEMICAL MECHANICAL POLISHING PROCESS 审中-公开
    回收包括使用化学机械抛光工艺的基板的方法

    公开(公告)号：US20080124930A1

    公开(公告)日：2008-05-29

    申请号：US11945359

    申请日：2007-11-27

    申请人： Jong Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

    发明人： Jong Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

    IPC分类号： H01L21/302

    CPC分类号： H01L21/02032 ,  C09G1/02 ,  H01L21/02024 ,  H01L21/02079

    摘要： In a method of recycling a substrate having an edge portion on which a stepped portion is formed, the substrate is chemically mechanically polished using a first slurry composition including fumed silica to remove the stepped portion. The substrate is then chemically mechanically polished using a second slurry composition including colloidal silica to improve the surface roughness of the substrate. The substrate having the edge region on which the stepped portion is formed may include a donor substrate used for manufacturing a silicon-on-insulator (SOI) substrate.

    摘要翻译： 在使具有形成阶梯部分的边缘部分的基板再循环的方法中，使用包括热解法二氧化硅的第一浆料组合物对基板进行化学机械抛光以去除台阶部分。 然后使用包含胶体二氧化硅的第二浆料组合物对衬底进行化学机械抛光，以改善衬底的表面粗糙度。 具有形成台阶部分的边缘区域的基板可以包括用于制造绝缘体上硅（SOI）衬底的施主衬底。

    Methods of forming stacked semiconductor devices with single-crystal semiconductor regions
    6.
    发明授权
    Methods of forming stacked semiconductor devices with single-crystal semiconductor regions 有权
    用单晶半导体区形成叠层半导体器件的方法

    公开(公告)号：US07932163B2

    公开(公告)日：2011-04-26

    申请号：US12029572

    申请日：2008-02-12

    申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

    发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/8221

    摘要： Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

    摘要翻译： 间隔开的接合表面形成在第一基底上。 第二衬底被结合到第一衬底的接合表面并且被切割以在第一衬底的相应的间隔的结合表面上的第二衬底上留下相应的半导体区域。 接合表面可以包括第一衬底上的至少一个绝缘区域的表面，并且至少一个有源器件可以形成在半导体区域中的至少一个中和/或至少一个半导体区域中。 器件隔离区域可以形成为与半导体区域中的至少一个相邻。

    Methods of Forming Stacked Semiconductor Devices with Single-Crystal Semiconductor Regions
    7.
    发明申请
    Methods of Forming Stacked Semiconductor Devices with Single-Crystal Semiconductor Regions 有权
    用单晶半导体区形成叠层半导体器件的方法

    公开(公告)号：US20080200009A1

    公开(公告)日：2008-08-21

    申请号：US12029572

    申请日：2008-02-12

    申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

    发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

    IPC分类号： H01L21/46

    CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/8221

    摘要： Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

    摘要翻译： 间隔开的接合表面形成在第一基底上。 第二衬底被结合到第一衬底的接合表面并且被切割以在第一衬底的相应的间隔的结合表面上的第二衬底上留下相应的半导体区域。 接合表面可以包括第一衬底上的至少一个绝缘区域的表面，并且至少一个有源器件可以形成在半导体区域中的至少一个中和/或至少一个半导体区域中。 器件隔离区域可以形成为与半导体区域中的至少一个相邻。

    Methods of forming semiconductor devices
    8.
    发明申请
    Methods of forming semiconductor devices 有权
    形成半导体器件的方法

    公开(公告)号：US20080200007A1

    公开(公告)日：2008-08-21

    申请号：US12070220

    申请日：2008-02-15

    申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229 ,  H01L21/3212

    摘要： A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

    摘要翻译： 一种形成半导体器件的方法包括：在半导体衬底上形成具有沟槽的图案; 在所述半导体器件上形成填充所述沟槽的半导体层; 使用第一平坦化工艺平坦化半导体层而不暴露图案; 在所述第一平坦化半导体层上进行外延生长工艺以形成晶体半导体层; 并且平坦化晶体半导体层直到图案被曝光以形成晶体半导体图案。

    Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same
    10.
    发明授权
    Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same 失效
    形成薄铁电体层的方法和制造其的半导体器件的制造方法

    公开(公告)号：US08124526B2

    公开(公告)日：2012-02-28

    申请号：US12503440

    申请日：2009-07-15

    申请人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    发明人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

    摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

    摘要翻译： 在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。 使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。 浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。