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    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    1.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    三维半导体器件及其制造方法

    公开(公告)号：US20120108048A1

    公开(公告)日：2012-05-03

    申请号：US13286384

    申请日：2011-11-01

    申请人： Jong Heun Lim ,  Jae Joo Shim ,  Hyo Jung Kim ,  Kyung Hyun Kim ,  Chang Sup Mun

    发明人： Jong Heun Lim ,  Jae Joo Shim ,  Hyo Jung Kim ,  Kyung Hyun Kim ,  Chang Sup Mun

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure.

    摘要翻译： 一种制造三维半导体存储器件的方法包括提供包括单元阵列区域和周边区域的衬底。 该方法还包括在基板的外围区域上的周边结构，其中外围结构包括外围电路并且被配置为暴露基板的单元阵列区域。 该方法还包括在基板的单元阵列区域上形成下单元结构，形成绝缘层以覆盖基板上的外围结构和下单元结构，使用外围结构的顶表面和下层单元平面化绝缘层 电池结构作为平坦化停止层，并在下电池结构上形成上电池结构。

    MULTIPLE MOLD STRUCTURE METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES
    4.
    发明申请
    MULTIPLE MOLD STRUCTURE METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES 有权
    制造垂直存储器件的多种模具结构方法

    公开(公告)号：US20130065386A1

    公开(公告)日：2013-03-14

    申请号：US13596621

    申请日：2012-08-28

    申请人： Hyo-Jung Kim ,  Dae-Hong Eom ,  Jong-Heun Lim ,  Myung-Jung Pyo ,  Byoung-Moon Yoon ,  Kyung-Hyun Kim

    发明人： Hyo-Jung Kim ,  Dae-Hong Eom ,  Jong-Heun Lim ,  Myung-Jung Pyo ,  Byoung-Moon Yoon ,  Kyung-Hyun Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L29/7926

    摘要： A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

    摘要翻译： 在包括第一和第二区域的基板上形成第一绝缘中间层。 第一绝缘中间层具有顶表面，其高度在第一区域中大于在第二区域中的高度。 形成第一平坦化停止层和第二绝缘夹层。 平面化第二绝缘层，直到第一平坦化停止层露出。 去除第二区域中的第一平坦化停止层和第一和第二绝缘夹层以露出衬底。 形成包括第一绝缘层图案，第一牺牲层图案和第二平坦化停止层图案的下模具结构。 第一绝缘层图案和第一牺牲层图案在基板上交替重复地形成，并且在第一绝缘层图案上形成第二平坦化停止层图案。

    Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics
    5.
    发明授权
    Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics 有权
    制造半导体器件的方法包括具有改进的缺陷密度和表面粗糙度特性的沟道层

    公开(公告)号：US07678625B2

    公开(公告)日：2010-03-16

    申请号：US11962742

    申请日：2007-12-21

    申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    IPC分类号： H01L21/84

    CPC分类号： H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

    摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

    摘要翻译： 制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。 单晶半导体层包括从其表面延伸的突起。 在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。 执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。 可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。 还讨论了制造叠层半导体存储器件的相关方法。

    NONVOLATILE MEMORY DEVICE AND A METHOD FOR FABRICATING THE SAME
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE AND A METHOD FOR FABRICATING THE SAME 有权
    非易失存储器件及其制造方法

    公开(公告)号：US20140048945A1

    公开(公告)日：2014-02-20

    申请号：US13927914

    申请日：2013-06-26

    申请人： Jong-Heun LIM ,  Hyo-Jung KIM ,  Ji-Woon IM ,  Kyung-Hyun KIM

    发明人： Jong-Heun LIM ,  Hyo-Jung KIM ,  Ji-Woon IM ,  Kyung-Hyun KIM

    IPC分类号： H01L23/48

    CPC分类号： H01L23/48 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

    摘要翻译： 一种非易失性存储器件，包括：包括单元阵列区域和连接区域的基板;形成在单元阵列区域上的电极结构和连接区域，并且包括多个层压电极;形成在电极结构中的第一凹部， 并且布置在单元阵列区域和形成在连接区域上的电极结构中的第二凹槽之间，以及形成在由第一凹部暴露的多个电极上的多个垂直布线。

    Methods of manufacturing semiconductor devices
    9.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08283248B2

    公开(公告)日：2012-10-09

    申请号：US13234558

    申请日：2011-09-16

    申请人： Tae-Hyun Kim ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

    发明人： Tae-Hyun Kim ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/11526 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L27/11573

    摘要： A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.

    摘要翻译： 一种制造半导体器件的方法包括：形成多个初步栅极结构，在多个预选栅极结构的侧壁上形成覆盖层图案，以及在多个预选栅极结构的顶表面上形成阻挡层，并且覆盖层 使得它们之间形成空隙。 该方法还包括去除阻挡层和覆盖层图案的上部，使得至少多个预选栅极结构的上侧壁被暴露，并且覆盖层图案的下部保留在预备的栅极结构的下侧壁上 门结构。 所述方法还包括在所述多个预选择门结构的至少上侧壁上形成导电层，使所述导电层与所述预选栅极结构反应，以及在其中形成具有气隙的绝缘层。

    Apparatus for polishing a wafer and method for detecting a polishing end point by the same
    10.
    发明授权
    Apparatus for polishing a wafer and method for detecting a polishing end point by the same 有权
    用于抛光晶片的装置和用于检测抛光终点的方法

    公开(公告)号：US08038508B2

    公开(公告)日：2011-10-18

    申请号：US12285852

    申请日：2008-10-15

    申请人： Jong-Heun Lim ,  Sung-Ho Shin ,  Bo-Un Yoon ,  Chang-Ki Hong

    发明人： Jong-Heun Lim ,  Sung-Ho Shin ,  Bo-Un Yoon ,  Chang-Ki Hong

    IPC分类号： B24B49/00

    CPC分类号： B24B9/065 ,  B24B21/02 ,  B24B37/013 ,  B24B49/12

    摘要： A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.

    摘要翻译： 晶片抛光装置包括在两个导辊之间延伸的研磨带，抛光带的与待抛光晶片的表面接触的第一表面，包括推动垫的抛光头，该推动垫适于将抛光带推向 要抛光的晶片的表面，邻近抛光带的彩色图像传感器，彩色图像传感器适于检测研磨带的彩色图像并输出与检测到的彩色图像相对应的信号，以及控制器，连接到 所述彩色图像传感器，所述控制器适于接收从彩色图像传感器输出的信号，并且确定由彩色图像传感器检测到的彩色图像的颜色何时改变指示抛光终点的彩色图像的变化。