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    High coupling memory cell
    1.
    发明授权
    High coupling memory cell 有权
    高耦合存储单元

    公开(公告)号：US07396720B2

    公开(公告)日：2008-07-08

    申请号：US10899913

    申请日：2004-07-27

    申请人： Sukesh Sandhu ,  Gurtej S. Sandhu

    发明人： Sukesh Sandhu ,  Gurtej S. Sandhu

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7881

    摘要： A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

    摘要翻译： 第一电介质层形成在衬底上。 用作浮栅的单层第一导电层形成在第一介电层上。 在第一导电层中形成槽，以增加浮栅与控制栅的电容耦合。 在浮栅层上形成隔间介电层。 在第二介电层上形成第二导电层以用作控制栅极。

    High coupling split-gate transistor
    3.
    发明授权
    High coupling split-gate transistor 有权
    高耦合分离栅晶体管

    公开(公告)号：US06614072B2

    公开(公告)日：2003-09-02

    申请号：US09976000

    申请日：2001-10-15

    申请人： Sukesh Sandhu ,  Gurtej S. Sandhu

    发明人： Sukesh Sandhu ,  Gurtej S. Sandhu

    IPC分类号： H01L27788

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A split-gate transistor having high coupling for use in flash memory, EPROMs, and EEPROMs. The transistor has a U-shaped floating gate and a U-shaped control gate, thereby significantly increasing the surface area of the gates and increasing the voltage coupling ratio. The high coupling permits the operation voltage to be reduced while increasing operation speed, and the configuration of the transistor gates allows their use in high density arrays without sacrificing speed or degrading operations. A process for forming such transistors is also disclosed, wherein a polysilicon layer is deposited and then etched so that nitride and polysilicon spacers may be formed in between portions of polysilicon which are then etched to form floating gates. The nitride portion of the spacers is removed, and then the dielectric and control gate layers are formed on the floating gates to yield an array of split-gate transistors.

    摘要翻译： 具有用于闪速存储器，EPROM和EEPROM的高耦合的分离栅极晶体管。 晶体管具有U形浮动栅极和U形控制栅极，从而显着增加栅极的表面积并增加电压耦合比。 高耦合允许在提高操作速度的同时降低工作电压，并且晶体管栅极的配置允许它们在高密度阵列中使用，而不会牺牲速度或降级操作。 还公开了一种用于形成这种晶体管的工艺，其中沉积多晶硅层然后进行蚀刻，以便可以在多晶硅的部分之间形成氮化物和多晶硅间隔物，然后蚀刻以形成浮栅。 去除间隔物的氮化物部分，然后在浮动栅极上形成电介质层和控制栅极层，以产生分离栅极晶体管阵列。

    HIGH COUPLING MEMORY CELL
    4.
    发明申请
    HIGH COUPLING MEMORY CELL 审中-公开
    高耦合存储单元

    公开(公告)号：US20110073929A1

    公开(公告)日：2011-03-31

    申请号：US12962012

    申请日：2010-12-07

    申请人： Sukesh Sandhu ,  Gurtej S. Sandhu

    发明人： Sukesh Sandhu ,  Gurtej S. Sandhu

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7881

    摘要： A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

    摘要翻译： 第一电介质层形成在衬底上。 用作浮栅的单层第一导电层形成在第一介电层上。 在第一导电层中形成槽，以增加浮栅与控制栅的电容耦合。 在浮栅层上形成隔间介电层。 在第二介电层上形成第二导电层以用作控制栅极。

    High coupling memory cell
    5.
    发明授权
    High coupling memory cell 有权
    高耦合存储单元

    公开(公告)号：US07749837B2

    公开(公告)日：2010-07-06

    申请号：US11486618

    申请日：2006-07-14

    申请人： Sukesh Sandhu ,  Gurtej S. Sandhu

    发明人： Sukesh Sandhu ,  Gurtej S. Sandhu

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7881

    摘要： A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

    摘要翻译： 第一电介质层形成在衬底上。 用作浮栅的单层第一导电层形成在第一介电层上。 在第一导电层中形成槽，以增加浮栅与控制栅的电容耦合。 在浮栅层上形成隔间介电层。 在第二介电层上形成第二导电层以用作控制栅极。

    High coupling split-gate transistor and method for its formation
    6.
    发明授权
    High coupling split-gate transistor and method for its formation 失效
    高耦合分离栅晶体管及其形成方法

    公开(公告)号：US06323085B1

    公开(公告)日：2001-11-27

    申请号：US09285667

    申请日：1999-04-05

    申请人： Sukesh Sandhu ,  Gurtej S. Sandhu

    发明人： Sukesh Sandhu ,  Gurtej S. Sandhu

    IPC分类号： H01L21336

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A split-gate transistor having high coupling for use in flash memory, EPROMs, and EEPROMs. The transistor has a U-shaped floating gate and a U-shaped control gate, thereby significantly increasing the surface area of the gates and increasing the voltage coupling ratio. The high coupling permits the operation voltage to be reduced while increasing operation speed, and the configuration of the transistor gates allows their use in high density arrays without sacrificing speed or degrading operations. A process for forming such transistors is also disclosed, wherein a polysilicon layer is deposited and then etched so that nitride and polysilicon spacers may be formed in between portions of polysilicon which are then etched to form floating gates. The nitride portion of the spacers is removed, and then the dielectric and control gate layers are formed on the floating gates to yield an array of split-gate transistors.

    摘要翻译： 具有用于闪速存储器，EPROM和EEPROM的高耦合的分离栅极晶体管。 晶体管具有U形浮动栅极和U形控制栅极，从而显着增加栅极的表面积并增加电压耦合比。 高耦合允许在提高操作速度的同时降低工作电压，并且晶体管栅极的配置允许它们在高密度阵列中使用，而不会牺牲速度或降级操作。 还公开了一种用于形成这种晶体管的工艺，其中沉积多晶硅层然后进行蚀刻，以便可以在多晶硅的部分之间形成氮化物和多晶硅间隔物，然后蚀刻以形成浮栅。 去除间隔物的氮化物部分，然后在浮动栅极上形成电介质层和控制栅极层，以产生分离栅极晶体管阵列。

    Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus
    7.
    发明授权
    Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus 有权
    在制造半导体器件期间形成亚光刻特征的方法和所得到的在制程装置

    公开(公告)号：US07413962B2

    公开(公告)日：2008-08-19

    申请号：US11440647

    申请日：2006-05-24

    申请人： Sukesh Sandhu ,  Gurtej S. Sandhu

    发明人： Sukesh Sandhu ,  Gurtej S. Sandhu

    IPC分类号： H01L21/76

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

    摘要： A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is etched to form an opening defined by first and second cross-sectional sidewalls in the hard mask layer. In one embodiment, the opening in the hard mask layer is formed at the minimum limits allowable by optical lithography. A conformal spacer layer is formed over the hard mask layer and on the sidewalls of the hard mask, then spacer etched to form first and second cross-sectional spacers along the first and second sidewalls in the patterned hard mask layer. The hard mask and spacers are preferably formed from amorphous carbon. The layer to be etched is etched using the hard mask layer and the spacers as a pattern, then the hard mask layer and spacers are removed.

    摘要翻译： 一种用于形成半导体器件的方法包括形成待蚀刻的层，然后在待蚀刻的层上形成硬掩模层。 硬掩模被蚀刻以形成由硬掩模层中的第一和第二横截面侧壁限定的开口。 在一个实施例中，硬掩模层中的开口以光学光刻所允许的最小限度形成。 在硬掩模层和硬掩模的侧壁上形成保形间隔层，然后间隔蚀刻以形成沿图案化硬掩模层中的第一和第二侧壁的第一和第二截面间隔物。 硬掩模和间隔物优选由无定形碳形成。 使用硬掩模层和间隔物作为图案来蚀刻待蚀刻的层，然后去除硬掩模层和间隔物。

    Pitch multiplication spacers and methods of forming the same
    8.
    发明授权
    Pitch multiplication spacers and methods of forming the same 有权
    间距倍增器及其形成方法

    公开(公告)号：US09099314B2

    公开(公告)日：2015-08-04

    申请号：US12827506

    申请日：2010-06-30

    申请人： Gurtej S. Sandhu ,  Kirk D. Prall

    发明人： Gurtej S. Sandhu ,  Kirk D. Prall

    IPC分类号： H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3205

    CPC分类号： H01L21/67063 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32053 ,  H01L21/32134

    摘要： Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

    摘要翻译： 在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。 相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。 选择性地去除未反应部分以留下独立间隔物的图案。 独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

    Electrically conductive laminate structure containing graphene region
    10.
    发明授权
    Electrically conductive laminate structure containing graphene region 有权
    导电层压结构

    公开(公告)号：US08946903B2

    公开(公告)日：2015-02-03

    申请号：US12833074

    申请日：2010-07-09

    申请人： Gurtej S. Sandhu

    发明人： Gurtej S. Sandhu

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01B13/00 ,  H01L21/768 ,  H01L23/532

    CPC分类号： H01L23/53276 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.

    摘要翻译： 一些实施例包括电互连。 互连可以包含层压结构，其具有夹在非石墨烯区域之间的石墨烯区域。 在一些实施例中，石墨烯和非石墨烯区域可以彼此嵌套。 在一些实施例中，电绝缘材料可以在层压结构的上表面之上，并且开口可以延伸穿过绝缘材料到层压结构的一部分。 导电材料可以在开口内并且与层压结构的非石墨烯区域中的至少一个电接触。 一些实施例包括形成电互连的方法，其中在沟槽内交替形成非石墨烯材料和石墨烯以形成嵌套的非石墨烯和石墨烯区域。