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6 条记录 (耗时 0.016 秒)

    Method for planarizing an insulator on a semiconductor substrate using ion implantation
    1.
    发明授权
    Method for planarizing an insulator on a semiconductor substrate using ion implantation 失效
    使用离子注入对半导体衬底上的绝缘体进行平面化的方法

    公开(公告)号：US5413953A

    公开(公告)日：1995-05-09

    申请号：US315706

    申请日：1994-09-30

    申请人： Sun-Chieh Chien ,  Ming-Hua Liu

    发明人： Sun-Chieh Chien ,  Ming-Hua Liu

    IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/768 ,  H01L21/76

    CPC分类号： H01L21/76213 ,  H01L21/31053 ,  H01L21/76819

    摘要： An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages. The invention also describes a method for forming more gradually sloping steps on the field oxide structure without using a sacrificial layer and a method for planarizing a CVD over a patterned conducting layer using photoresist or spin-on-glass as the sacrificial implant layer.

    摘要翻译： 实现了在硅衬底上制造平面场氧化物结构的改进方法。 该方法包括通过使用硅的LOCal氧化（LOCOS）工艺形成场氧化物，其中器件区域被氮化硅层防止氧化。 使用诸如CVD氧化物，氧氮化物或抗反射涂层（ARC）层的牺牲注入层来填充氮化硅和场氧化物结构之间的间隙，并使衬底表面更平坦。 然后将衬底表面注入穿过牺牲注入层的As75或p31离子，并在场氧化物上形成植入物损伤层。 在湿蚀刻中蚀刻更快的植入物损伤层选择性地移除，从而形成更平坦的场氧化物结构。 该方法不需要在硅衬底中蚀刻凹槽，因此具有一定的可靠性和成本优点。 本发明还描述了一种用于在不使用牺牲层的情况下在场氧化物结构上形成更多逐渐倾斜的步骤的方法，以及使用光致抗蚀剂或旋涂玻璃作为牺牲注入层在图案化导电层上平坦化CVD的方法。

    Method for forming a planar field oxide (fox) on substrates for integrated circuit
    2.
    发明授权
    Method for forming a planar field oxide (fox) on substrates for integrated circuit 失效
    在集成电路基板上形成平面场氧化物（fox）的方法

    公开(公告)号：US5554560A

    公开(公告)日：1996-09-10

    申请号：US315772

    申请日：1994-09-30

    申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Ming-Hua Liu

    发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Ming-Hua Liu

    IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76202 ,  H01L21/31055

    摘要： An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial leveling layer, such as spin-on-glass (SOG) or a anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The leveling layer is then etched back non-selectively by plasma etching to planarize the portion of the field oxide extending above the substrate surface. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.

    摘要翻译： 实现了在硅衬底上制造平面场氧化物结构的改进方法。 该方法包括通过使用硅的LOCal氧化（LOCOS）工艺形成场氧化物，其中器件区域被氮化硅层防止氧化。 使用诸如旋涂玻璃（SOG）或抗反射涂层（ARC）层的牺牲调平层填充氮化硅和场氧化物结构之间的间隙，并使基板表面更平坦。 然后通过等离子体蚀刻非选择性地蚀刻流平层，以平坦化在衬底表面上方延伸的场氧化物的部分。 该方法不需要在硅衬底中蚀刻凹槽，因此具有一定的可靠性和成本优点。

    Method of forming a self-aligned contact of a DRAM cell
    4.
    发明授权
    Method of forming a self-aligned contact of a DRAM cell 失效
    形成DRAM单元的自对准接触的方法

    公开(公告)号：US5885895A

    公开(公告)日：1999-03-23

    申请号：US826143

    申请日：1997-03-27

    申请人： Ming-Hua Liu ,  Chuck Chen

    发明人： Ming-Hua Liu ,  Chuck Chen

    IPC分类号： H01L21/60 ,  H01L21/8242

    CPC分类号： H01L27/10873 ,  H01L21/76897

    摘要： A method of forming a self-aligned contact of a DRAM cell includes providing a substrate having a MOS transistor. The MOS transistor includes a gate and a source/drain region. A first insulating layer, a second insulating layer and a third insulating layer are formed over the surface of the substrate in succession. The third insulating layer is planarized. A contact window mask is formed above the third insulating layer. Using the contact window mask as a cover, the third insulating layer is removed using anisotropic dry etching and isotropic wet etching. Then, a portion of the second insulating layer and a portion of the first insulating layer are removed sequentially to expose the source/drain region so that a self-aligned contact is formed.

    摘要翻译： 形成DRAM单元的自对准接触的方法包括提供具有MOS晶体管的衬底。 MOS晶体管包括栅极和源极/漏极区域。 在基板的表面上依次形成第一绝缘层，第二绝缘层和第三绝缘层。 第三绝缘层被平坦化。 在第三绝缘层上形成接触窗口罩。 使用接触窗口掩模作为覆盖物，使用各向异性干法蚀刻和各向同性湿法蚀刻去除第三绝缘层。 然后，依次除去第二绝缘层的一部分和第一绝缘层的一部分，露出源/漏区，从而形成自对准接触。

    Method of forming self-aligned buried contact
    5.
    发明授权
    Method of forming self-aligned buried contact 失效
    形成自对准埋层接触的方法

    公开(公告)号：US5576242A

    公开(公告)日：1996-11-19

    申请号：US573962

    申请日：1995-12-15

    申请人： Ming-Hua Liu

    发明人： Ming-Hua Liu

    IPC分类号： H01L21/28 ,  H01L21/44

    CPC分类号： H01L21/28

    摘要： Disclosed is a method of forming self-aligned buried contact implementing self-alignment technology into buried contact process to prevent failure of semiconductor elements due to disconnection of wiring which is caused by misalignment. This is done by forming a sidewall spacer in the recess on the buried contact region. The tolerance of misalignment is greatly increased because a polysilicon layer will contact with the buried contact region if the polysilicon layer could contact the sidewall spacer.

    摘要翻译： 公开了一种将自对准技术形成为自对准技术的埋入接触工艺的方法，以防止由于未对准引起的布线断开导致的半导体元件的故障。 这通过在掩埋接触区域上的凹部中形成侧壁间隔物来完成。 如果多晶硅层可以接触侧壁间隔物，则由于多晶硅层将与埋入接触区域接触，因此大大增加了未对准的公差。

    Method for fabricating lightly doped drain metal oxide semiconductor field effect transistor
    6.
    发明授权
    Method for fabricating lightly doped drain metal oxide semiconductor field effect transistor 失效
    轻掺杂漏极金属氧化物半导体场效应晶体管的制造方法

    公开(公告)号：US5698461A

    公开(公告)日：1997-12-16

    申请号：US614346

    申请日：1996-03-12

    申请人： Ming-Hua Liu

    发明人： Ming-Hua Liu

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/335

    CPC分类号： H01L29/66583 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7836

    摘要： A lightly doped drain (LDD) metal oxide semiconductor field effect transistor (MOSFET). Field oxide is used as a hard mask for a total-overlap polysilicon (TOP) gate which minimizes hot-carrier degradation, so that a soft-mask step is saved. The field oxide is used also as a hard mask for surface counter-doping which reduces gate-induced drain leakage, and in making a punch-through stop which reduces drain-induced barrier low and short channel effect.

    摘要翻译： 轻掺杂漏极（LDD）金属氧化物半导体场效应晶体管（MOSFET）。 场氧化物用作全重叠多晶硅（TOP）栅极的硬掩模，其使热载流子劣化最小化，从而节省了软掩模步骤。 场氧化物还用作用于表面反掺杂的硬掩模，其减少了栅极引起的漏极泄漏，并且进行了穿通停止，这减少了漏极引起的屏障低和短沟道效应。