公开(公告)号：US6017799A

公开(公告)日：2000-01-25

申请号：US40553

申请日：1998-03-18

申请人： Sun-Chieh Chien ,  Peter Hsue ,  Der-Yuan Wu

发明人： Sun-Chieh Chien ,  Peter Hsue ,  Der-Yuan Wu

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/10894

摘要： A method of fabricating a dynamic random memory. On a semiconductor substrate comprising a memory cell region and a periphery circuit region, a first field implantation and a first anti-punch through implantation are performed. Using a photo-resist layer formed to cover the memory cell region as a mask, the periphery circuit region is performed with a second field implantation and a second anti-punch through implantation.

摘要翻译： 一种制造动态随机存储器的方法。 在包括存储单元区域和外围电路区域的半导体衬底上，执行第一场注入和第一抗穿透注入。 使用形成为覆盖存储单元区域作为掩模的光致抗蚀剂层，通过第二场注入和第二抗穿透注入来执行外围电路区域。

公开(公告)号：US6121085A

公开(公告)日：2000-09-19

申请号：US9508

申请日：1998-01-20

申请人： Chia-Wen Liang ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Jason Jenq

发明人： Chia-Wen Liang ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Jason Jenq

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10852

摘要： A method of making contact openings for memory cell units of DRAM IC devices is disclosed. The contact opening is used to connect the cell transistor source/drain terminal to the storage capacitor electrode located substantially above. The method includes the step of first patterning the initial opening in a shielding layer for the contact opening. The diameter of the initial opening is then reduced by the formation of sidewall spacers in initial opening. The initial opening in the shielding layer is then used to implement the etching for the formation of the contact opening. Due to reduced size of the contact opening, short-circuiting situations arising between the via formed in the contact opening and the bit lines next to the via as a result of misalignment in the process of fabrication can be reduced, thereby improving the device fabrication yield rates.

摘要翻译： 公开了一种制造DRAM IC器件的存储单元的接触开口的方法。 接触开口用于将单元晶体管源极/漏极端子连接到大致位于上方的存储电容器电极。 该方法包括首先在接触开口的屏蔽层中构图初始开口的步骤。 然后通过在初始开口中形成侧壁间隔来减小初始开口的直径。 然后使用屏蔽层中的初始开口来实现用于形成接触开口的蚀刻。 由于接触开口的尺寸减小，可以减少在制造工艺中由于在接触开口中形成的通孔与通孔旁边的位线之间产生的短路情况，从而提高器件的制造成品率 价格。

公开(公告)号：US6110827A

公开(公告)日：2000-08-29

申请号：US655074

申请日：1996-06-03

申请人： Sun-Chieh Chien ,  Der-Yuan Wu ,  Kun-Cho Chen

发明人： Sun-Chieh Chien ,  Der-Yuan Wu ,  Kun-Cho Chen

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76819 ,  Y10S438/959

摘要： A planarization method for self-aligned contact process which is suitable for use in DRAM processing. Prior to the formation of the bottom terminal layer of the capacitor, the substrate surface is first planarized, thus avoiding stringer effects and related bridging problems arising from an undulating surface profile, during subsequent etching of the defined pattern. Also according to the method of this invention, by covering the silicon substrate that has MOS transistors laid on top with first a deposition of an oxide layer, then an etch discriminatory layer, and finally a planarization layer, a substrate with a smooth, plane surface is obtained.

摘要翻译： 用于自对准接触工艺的平面化方法，适用于DRAM处理。 在形成电容器的底部端子层之前，首先将衬底表面平坦化，从而在随后蚀刻限定的图案期间避免由起伏的表面轮廓引起的纵梁效应和相关的桥接问题。 此外，根据本发明的方法，首先通过覆盖首先沉积氧化物层的MOS晶体管的硅衬底，然后蚀刻鉴别层，最后是平坦化层，具有平滑的平面表面的衬底 获得。

公开(公告)号：US06432768B1

公开(公告)日：2002-08-13

申请号：US09510970

申请日：2000-02-21

申请人： Sun-Chieh Chien ,  Der-Yuan Wu

发明人： Sun-Chieh Chien ,  Der-Yuan Wu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10873 ,  H01L29/665

摘要： A method of fabricating a memory device and a logic device on the same chip is described, wherein the memory device has a first gate on a first region of the chip, and wherein the logic device has a second gate with a sidewall on a second region of the chip. A conductive layer and a first suicide layer are sequentially formed over the first and the second regions of the chip. Over the first region of the chip, the first silicide layer and the conductive layer are patterned to form the first gate. Ions are first implanted into the first region of the chip, by using the first gate as a mask, to form a first doped region. A dielectric layer is formed to cap the first gate, the first doped region and the first region of the chip. The first silicide layer over the second region of the chip is removed. Over the second region of the chip, the conductive layer is patterned to form the second gate. Ions are second implanted into the second region of the chip, by using the second gate as a mask, to form a second doped region.

摘要翻译： 描述了在同一芯片上制造存储器件和逻辑器件的方法，其中存储器件在芯片的第一区域上具有第一栅极，并且其中逻辑器件具有在第二区域上具有侧壁的第二栅极 的芯片。 在芯片的第一和第二区域上依次形成导电层和第一硅化物层。 在芯片的第一区域上，第一硅化物层和导电层被图案化以形成第一栅极。 通过使用第一栅极作为掩模，首先将离子注入到芯片的第一区域中，以形成第一掺杂区域。 形成介电层，以覆盖芯片的第一栅极，第一掺杂区域和第一区域。 去除芯片第二区域上的第一硅化物层。 在芯片的第二区域上，对导电层进行图案化以形成第二栅极。 通过使用第二栅极作为掩模，将第二注入到芯片的第二区域中，以形成第二掺杂区域。

公开(公告)号：US6030867A

公开(公告)日：2000-02-29

申请号：US975708

申请日：1997-11-21

申请人： Sun-Chieh Chien ,  Jason Jenq ,  Der-Yuan Wu ,  Chia-Wen Liang

发明人： Sun-Chieh Chien ,  Jason Jenq ,  Der-Yuan Wu ,  Chia-Wen Liang

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L24/11 ,  H01L27/10852 ,  H01L28/84 ,  H01L21/76895 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

摘要： The DRAM cell is formed by covering the cell's transfer FET with a conformal insulating layer. A self aligned contact etch removes a portion of the conformal insulating layer from above a first source/drain region of the FET and then a first polysilicon layer is deposited over the device. Etching defines a polysilicon pad from the first polysilicon layer with edges of the polysilicon pad disposed over the gate electrode and an adjacent wiring line. A thick, planarized second insulating layer is provided over the device, filling the volume defined by the locally cupped surface of the polysilicon pad. Etching is performed to remove a portion of the planarized insulating layer using the pad polysilicon layer as an etch stop for the process. A second, thick polysilicon layer is next provided to fill the cavity and the layer is patterned to laterally define the lower capacitor electrode. Hemispherical grained silicon (HSG-Si) is deposited on the surface of the patterned polysilicon layer and an etch back process is used to transfer the topology of the HSG-Si layer to the underlying polysilicon. Further processing provides a capacitor dielectric and an upper electrode.

摘要翻译： 通过用保形绝缘层覆盖电池的转移FET来形成DRAM单元。 自对准接触蚀刻从FET的第一源极/漏极区上方去除保形绝缘层的一部分，然后在器件上沉积第一多晶硅层。 蚀刻定义了来自第一多晶硅层的多晶硅焊盘，其中多晶硅焊盘的边缘设置在栅电极和相邻布线之上。 在该器件上方提供厚的平坦化的第二绝缘层，填充由多晶硅垫的局部杯形表面限定的体积。 使用焊盘多晶硅层作为该工艺的蚀刻停止来执行蚀刻以去除平坦化绝缘层的一部分。 接下来提供第二厚的多晶硅层以填充空腔，并且对该层进行图案化以横向限定下部电容器电极。 半球形晶粒硅（HSG-Si）沉积在图案化的多晶硅层的表面上，并且使用回蚀工艺将HSG-Si层的拓扑转移到下面的多晶硅。 进一步的处理提供电容器电介质和上电极。

公开(公告)号：US06140201A

公开(公告)日：2000-10-31

申请号：US172407

申请日：1998-10-14

申请人： J. S. Jason Jenq ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Chuan-Fu Wang

发明人： J. S. Jason Jenq ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Chuan-Fu Wang

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/92 ,  H01L21/3143 ,  H01L27/10852

摘要： A method for fabricating a cylinder capacitor of a DRAM cell that starts with forming a first oxide layer and then a doped first polysilicon layer on a substrate, patterning the first polysilicon layer to form a first opening that exposes the first oxide layer, forming a polysilicon spacer at the laterals of the first opening. Then, a portion of the first oxide layer is removed to expose the substrate by using the polysilicon spacer and the first polysilicon layer as a mask. A doped second polysilicon layer is formed on the first polysilicon layer and in the first opening. A portion of the second polysilicon layer is removed to form a second opening. A oxide spacer is formed on the laterals of the second opening, and is used as mask to remove a portion of the second polysilicon layer for forming a lower electrode. A dielectric layer and then a third polysilicon layer are formed on the lower electrode after the silicon oxide spacer is removed, wherein the third polysilicon is an upper electrode.

摘要翻译： 一种用于制造DRAM单元的圆柱电容器的方法，其开始于形成第一氧化物层，然后在衬底上形成掺杂的第一多晶硅层，图案化第一多晶硅层以形成暴露第一氧化物层的第一开口，形成多晶硅 间隔在第一个开口的边缘。 然后，通过使用多晶硅间隔物和第一多晶硅层作为掩模，去除第一氧化物层的一部分以暴露衬底。 掺杂的第二多晶硅层形成在第一多晶硅层和第一开口中。 去除第二多晶硅层的一部分以形成第二开口。 在第二开口的侧壁上形成氧化物间隔物，并且用作掩模以去除用于形成下电极的第二多晶硅层的一部分。 在除去氧化硅间隔物之后，在下电极上形成电介质层，然后形成第三多晶硅层，其中第三多晶硅是上电极。

公开(公告)号：US06833318B2

公开(公告)日：2004-12-21

申请号：US10065803

申请日：2002-11-20

申请人： Chun-Jen Weng ,  Juan-Yi Chen ,  Hong-Tsz Pan ,  Cedric Lee ,  Der-Yuan Wu ,  Jackson Lin ,  Yeong-Song Yen ,  Lawrence Lin ,  Ying-Chung Tseng

发明人： Chun-Jen Weng ,  Juan-Yi Chen ,  Hong-Tsz Pan ,  Cedric Lee ,  Der-Yuan Wu ,  Jackson Lin ,  Yeong-Song Yen ,  Lawrence Lin ,  Ying-Chung Tseng

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

摘要翻译： 提供间隙填充过程。 提供其上具有介电层的基板。 电介质层中有一个开口。 在电介质层和开口内部形成间隙填充材料层。 间隙填充材料的一部分从间隙填充材料层去除以暴露电介质层。 进行间隙填充材料层和电介质层的表面的间隙填充材料处理以使间隙填充材料层平坦化，从而在间隙填充材料上形成随后形成的底部抗反射涂层或材料层 层可以具有高度的平面度。

公开(公告)号：US06667534B1

公开(公告)日：2003-12-23

申请号：US10197861

申请日：2002-07-19

申请人： Der-Yuan Wu ,  Chiu-Te Lee

发明人： Der-Yuan Wu ,  Chiu-Te Lee

IPC分类号： H01L2943

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in the prior art, the cost of the fuse manufacturing is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

摘要翻译： 在本发明中公开了一种铜熔丝结构及其制造方法。 通过使用内部铜金属层作为保险丝，根据本发明的铜熔丝可以用激光修复工具容易地拉链。 此外，可以使用根据本发明的方法来识别焊盘上的开口和半导体结构的熔丝。 此外，与现有技术中的上铝层形成的保险丝相反，根据本发明的方法，通过制造具有内铜层的保险丝，熔丝制造的成本较低。

公开(公告)号：US06753244B2

公开(公告)日：2004-06-22

申请号：US10426787

申请日：2003-05-01

申请人： Der-Yuan Wu ,  Chiu-Te Lee

发明人： Der-Yuan Wu ,  Chiu-Te Lee

IPC分类号： H01L2144

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in the prior art, the cost of the fuse manufacturing is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

摘要翻译： 在本发明中公开了一种铜熔丝结构及其制造方法。 通过使用内部铜金属层作为保险丝，根据本发明的铜熔丝可以用激光修复工具容易地拉链。 此外，可以使用根据本发明的方法来识别焊盘上的开口和半导体结构的熔丝。 此外，与现有技术中的上铝层形成的保险丝相反，根据本发明的方法，通过制造具有内铜层的保险丝，熔丝制造的成本较低。

公开(公告)号：US06392924B1

公开(公告)日：2002-05-21

申请号：US09828376

申请日：2001-04-06

申请人： Chih-Cheng Liu ,  Der-Yuan Wu

发明人： Chih-Cheng Liu ,  Der-Yuan Wu

IPC分类号： G11C1100

CPC分类号： H01L27/222 ,  G11C11/15 ,  G11C11/16

摘要： The array includes: a plurality of pseudo spin valve (PSV) cells; a plurality of parallel bit lines, wherein a plurality of bit lines are straight lines and located under the plurality of pseudo spin valve (PSV) cells; a plurality of parallel word lines, wherein a plurality of word lines are continuous-bended lines having a first straight line, a second straight line and a third straight line. These straight lines of the word lines are orthogonal each other, wherein the first straight line and the third straight line are parallel. The first straight line and the third straight line are individually orthogonal with the direction of the bit lines. Furthermore, the second straight lines of the word lines are individually located on the pseudo spin valve (PSV) cells, and the second straight lines are parallel with the direction of the bit lines, so as to increase the magnetresistance ratio.

摘要翻译： 阵列包括：多个假自旋阀（PSV）单元; 多个并行位线，其中多个位线是直线并位于所述多个伪自旋阀（PSV）单元之下; 多个平行字线，其中多个字线是具有第一直线，第二直线和第三直线的连续弯曲线。 字线的这些直线彼此正交，其中第一直线和第三直线平行。 第一直线和第三直线与位线的方向分别正交。 此外，字线的第二直线分别位于伪自旋阀（PSV）单元上，并且第二直线与位线的方向平行，以增加磁阻比。