公开(公告)号：US08644074B2

公开(公告)日：2014-02-04

申请号：US13107139

申请日：2011-05-13

申请人： Sung-Il Chang ,  Changseok Kang ,  Chan Park ,  Byeong-In Choe

发明人： Sung-Il Chang ,  Changseok Kang ,  Chan Park ,  Byeong-In Choe

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/0483

摘要： A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.

摘要翻译： 一种防止程序干扰的非易失性存储器件，其程序方法和包括非易失性存储器件和程序方法的存储器系统。 非易失性存储器件包括存储单元阵列; 连接到存储单元阵列中的NAND串的第一和第二字线; 连接到NAND串的第三字线，第三字线设置在第一和第二字线之间; 温度传感器，被配置为测量所述非易失性存储装置的温度; 以及电压发生器，被配置为产生第一和第二通过电压和编程电压，并且根据测量的温度来控制第一和第二通过电压中的至少一个的电压电平。 当执行编程操作时，将编程电压施加到第三字线，将第一通过电压施加到第一字线，将第二通过电压施加到第二字线。

公开(公告)号：US20110286274A1

公开(公告)日：2011-11-24

申请号：US13107139

申请日：2011-05-13

申请人： Sung-Il Chang ,  Changseok Kang ,  Chan Park ,  Byeong-In Choe

发明人： Sung-Il Chang ,  Changseok Kang ,  Chan Park ,  Byeong-In Choe

IPC分类号： G11C16/10

CPC分类号： G11C16/3418 ,  G11C16/0483

摘要： A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.

摘要翻译： 一种防止程序干扰的非易失性存储器件，其程序方法和包括非易失性存储器件和程序方法的存储器系统。 非易失性存储器件包括存储单元阵列; 连接到存储单元阵列中的NAND串的第一和第二字线; 连接到NAND串的第三字线，第三字线设置在第一和第二字线之间; 温度传感器，被配置为测量所述非易失性存储装置的温度; 以及电压发生器，被配置为产生第一和第二通过电压和编程电压，并且根据测量的温度来控制第一和第二通过电压中的至少一个的电压电平。 当执行编程操作时，将编程电压施加到第三字线，将第一通过电压施加到第一字线，将第二通过电压施加到第二字线。

公开(公告)号：US08804417B2

公开(公告)日：2014-08-12

申请号：US13157343

申请日：2011-06-10

申请人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

发明人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/22

CPC分类号： G11C16/10 ,  G11C16/3418

摘要： A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.

摘要翻译： 一种包括虚拟存储单元的非易失性存储器件及其编程方法，其中非易失性存储器件包括一个虚拟存储单元和与该虚拟存储单元串联连接的多个存储单元。 非易失性存储装置根据执行程序操作时的多个存储单元中的所选择的存储单元与虚拟存储单元之间的距离，设定提供给虚拟存储单元的电压。

公开(公告)号：US20110305079A1

公开(公告)日：2011-12-15

申请号：US13157343

申请日：2011-06-10

申请人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

发明人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/3418

摘要： A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.

摘要翻译： 一种包括虚拟存储单元的非易失性存储器件及其编程方法，其中非易失性存储器件包括一个虚拟存储单元和与该虚拟存储单元串联连接的多个存储单元。 非易失性存储装置根据执行程序操作时的多个存储单元中的所选择的存储单元与虚拟存储单元之间的距离，设定提供给虚拟存储单元的电压。

公开(公告)号：US20120003828A1

公开(公告)日：2012-01-05

申请号：US13173321

申请日：2011-06-30

申请人： Sung-Il Chang ,  Changseok Kang ,  Byeong-In Choe

发明人： Sung-Il Chang ,  Changseok Kang ,  Byeong-In Choe

IPC分类号： H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/792

摘要： A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成包括牺牲层和选择栅极层的叠层结构，形成穿透层叠结构的穿透区域，在选择栅极层的侧壁上形成选择栅极绝缘层， 穿透区域，并且在穿透区域中形成活性图案。 该方法还包括通过去除牺牲层并在活性图案的暴露部分上形成信息存储层来暴露活性图案的一部分。

公开(公告)号：US20110205802A1

公开(公告)日：2011-08-25

申请号：US13029947

申请日：2011-02-17

申请人： Byeong-In CHOE ,  Sung-Il Chang ,  Changseok Kang

发明人： Byeong-In CHOE ,  Sung-Il Chang ,  Changseok Kang

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： Provided are a nonvolatile memory device and a method of reading the same. The nonvolatile memory device includes: a memory cell; a transistor disposed between a common source line and the memory cell; and a control logic for controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation. The method includes: applying a read voltage to the memory cell; and controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line.

摘要翻译： 提供一种非易失性存储器件及其读取方法。 非易失性存储器件包括：存储单元; 设置在公共源极线和存储器单元之间的晶体管; 以及用于控制晶体管的偏置电压以减少在读取操作期间流入公共源极线的电流量的控制逻辑。 该方法包括：向存储单元施加读取电压; 以及控制晶体管的偏置电压以减少流入公共源极线的电流量。

公开(公告)号：US08379456B2

公开(公告)日：2013-02-19

申请号：US12901605

申请日：2010-10-11

申请人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Youngwoo Park ,  Jongsun Sel ,  Jintaek Park

发明人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Youngwoo Park ,  Jongsun Sel ,  Jintaek Park

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/10

摘要： Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation.

摘要翻译： 提供了非易失性存储器件及其操作方法。 非易失性存储器件包括：连接到虚拟位线的虚拟单元; 以及在编程操作期间向虚拟位线提供虚拟位线电压的虚拟位线偏置电路，其中，由于虚拟位线电压，至少一个虚设单元被编程为具有低于顶部的阈值电压 在程序运行期间高于擦除状态。

公开(公告)号：US20110085385A1

公开(公告)日：2011-04-14

申请号：US12901605

申请日：2010-10-11

申请人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Youngwoo Park ,  Jongsun Sel ,  Jintaek Park

发明人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Youngwoo Park ,  Jongsun Sel ,  Jintaek Park

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/10

摘要： Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation.

摘要翻译： 提供了非易失性存储器件及其操作方法。 非易失性存储器件包括：连接到虚拟位线的虚拟单元; 以及在编程操作期间向虚拟位线提供虚拟位线电压的虚拟位线偏置电路，其中，由于虚拟位线电压，至少一个虚设单元被编程为具有低于顶部的阈值电压 在程序运行期间高于擦除状态。

公开(公告)号：US20120230103A1

公开(公告)日：2012-09-13

申请号：US13289463

申请日：2011-11-04

申请人： Byeong-In Choe ,  Changseok Kang ,  Woonkyung Lee

发明人： Byeong-In Choe ,  Changseok Kang ,  Woonkyung Lee

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.

摘要翻译： 根据示例性实施例，非易失性存储器件包括衬底，从衬底垂直延伸的至少一个串和经由至少一个位线连接到至少一个串的位线电流控制电路。 至少一个串可以包括含有多晶硅的通道。 位线电流控制电路可以被配置为根据温度的降低来增加提供给位线的电流量，使得当温度降低时流过至少一个串的通道的电流增加。

公开(公告)号：US08724394B2

公开(公告)日：2014-05-13

申请号：US13289463

申请日：2011-11-04

申请人： Byeong-In Choe ,  Changseok Kang ,  Woonkyung Lee

发明人： Byeong-In Choe ,  Changseok Kang ,  Woonkyung Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.

摘要翻译： 根据示例性实施例，非易失性存储器件包括衬底，从衬底垂直延伸的至少一个串和经由至少一个位线连接到至少一个串的位线电流控制电路。 至少一个串可以包括含有多晶硅的通道。 位线电流控制电路可以被配置为根据温度的降低来增加提供给位线的电流量，使得当温度降低时流过至少一个串的通道的电流增加。