公开(公告)号：US20120003828A1

公开(公告)日：2012-01-05

申请号：US13173321

申请日：2011-06-30

申请人： Sung-Il Chang ,  Changseok Kang ,  Byeong-In Choe

发明人： Sung-Il Chang ,  Changseok Kang ,  Byeong-In Choe

IPC分类号： H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/792

摘要： A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成包括牺牲层和选择栅极层的叠层结构，形成穿透层叠结构的穿透区域，在选择栅极层的侧壁上形成选择栅极绝缘层， 穿透区域，并且在穿透区域中形成活性图案。 该方法还包括通过去除牺牲层并在活性图案的暴露部分上形成信息存储层来暴露活性图案的一部分。

公开(公告)号：US08644074B2

公开(公告)日：2014-02-04

申请号：US13107139

申请日：2011-05-13

申请人： Sung-Il Chang ,  Changseok Kang ,  Chan Park ,  Byeong-In Choe

发明人： Sung-Il Chang ,  Changseok Kang ,  Chan Park ,  Byeong-In Choe

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/0483

摘要： A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.

摘要翻译： 一种防止程序干扰的非易失性存储器件，其程序方法和包括非易失性存储器件和程序方法的存储器系统。 非易失性存储器件包括存储单元阵列; 连接到存储单元阵列中的NAND串的第一和第二字线; 连接到NAND串的第三字线，第三字线设置在第一和第二字线之间; 温度传感器，被配置为测量所述非易失性存储装置的温度; 以及电压发生器，被配置为产生第一和第二通过电压和编程电压，并且根据测量的温度来控制第一和第二通过电压中的至少一个的电压电平。 当执行编程操作时，将编程电压施加到第三字线，将第一通过电压施加到第一字线，将第二通过电压施加到第二字线。

公开(公告)号：US20110286274A1

公开(公告)日：2011-11-24

申请号：US13107139

申请日：2011-05-13

申请人： Sung-Il Chang ,  Changseok Kang ,  Chan Park ,  Byeong-In Choe

发明人： Sung-Il Chang ,  Changseok Kang ,  Chan Park ,  Byeong-In Choe

IPC分类号： G11C16/10

CPC分类号： G11C16/3418 ,  G11C16/0483

摘要： A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.

摘要翻译： 一种防止程序干扰的非易失性存储器件，其程序方法和包括非易失性存储器件和程序方法的存储器系统。 非易失性存储器件包括存储单元阵列; 连接到存储单元阵列中的NAND串的第一和第二字线; 连接到NAND串的第三字线，第三字线设置在第一和第二字线之间; 温度传感器，被配置为测量所述非易失性存储装置的温度; 以及电压发生器，被配置为产生第一和第二通过电压和编程电压，并且根据测量的温度来控制第一和第二通过电压中的至少一个的电压电平。 当执行编程操作时，将编程电压施加到第三字线，将第一通过电压施加到第一字线，将第二通过电压施加到第二字线。

公开(公告)号：US08804417B2

公开(公告)日：2014-08-12

申请号：US13157343

申请日：2011-06-10

申请人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

发明人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/22

CPC分类号： G11C16/10 ,  G11C16/3418

摘要： A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.

摘要翻译： 一种包括虚拟存储单元的非易失性存储器件及其编程方法，其中非易失性存储器件包括一个虚拟存储单元和与该虚拟存储单元串联连接的多个存储单元。 非易失性存储装置根据执行程序操作时的多个存储单元中的所选择的存储单元与虚拟存储单元之间的距离，设定提供给虚拟存储单元的电压。

公开(公告)号：US20110305079A1

公开(公告)日：2011-12-15

申请号：US13157343

申请日：2011-06-10

申请人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

发明人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Byeong-In Choe

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/3418

摘要： A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.

摘要翻译： 一种包括虚拟存储单元的非易失性存储器件及其编程方法，其中非易失性存储器件包括一个虚拟存储单元和与该虚拟存储单元串联连接的多个存储单元。 非易失性存储装置根据执行程序操作时的多个存储单元中的所选择的存储单元与虚拟存储单元之间的距离，设定提供给虚拟存储单元的电压。

公开(公告)号：US20120230103A1

公开(公告)日：2012-09-13

申请号：US13289463

申请日：2011-11-04

申请人： Byeong-In Choe ,  Changseok Kang ,  Woonkyung Lee

发明人： Byeong-In Choe ,  Changseok Kang ,  Woonkyung Lee

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.

摘要翻译： 根据示例性实施例，非易失性存储器件包括衬底，从衬底垂直延伸的至少一个串和经由至少一个位线连接到至少一个串的位线电流控制电路。 至少一个串可以包括含有多晶硅的通道。 位线电流控制电路可以被配置为根据温度的降低来增加提供给位线的电流量，使得当温度降低时流过至少一个串的通道的电流增加。

公开(公告)号：US08724394B2

公开(公告)日：2014-05-13

申请号：US13289463

申请日：2011-11-04

申请人： Byeong-In Choe ,  Changseok Kang ,  Woonkyung Lee

发明人： Byeong-In Choe ,  Changseok Kang ,  Woonkyung Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.

摘要翻译： 根据示例性实施例，非易失性存储器件包括衬底，从衬底垂直延伸的至少一个串和经由至少一个位线连接到至少一个串的位线电流控制电路。 至少一个串可以包括含有多晶硅的通道。 位线电流控制电路可以被配置为根据温度的降低来增加提供给位线的电流量，使得当温度降低时流过至少一个串的通道的电流增加。

公开(公告)号：US08599622B2

公开(公告)日：2013-12-03

申请号：US13176950

申请日：2011-07-06

申请人： Juhyung Kim ,  Changseok Kang ,  Hansoo Kim ,  Byeong-In Choe

发明人： Juhyung Kim ,  Changseok Kang ,  Hansoo Kim ,  Byeong-In Choe

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/32

摘要： An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase operation changes a level of a word line voltage applied to word lines during the erase execution interval, a length of the delay time, or a level of the word line voltage applied to the word lines during the delay time.

摘要翻译： 一种电荷捕捉闪存器件的擦除方法，该方法包括接收温度检测结果，并且基于温度检测结果执行擦除操作，其中擦除操作包括擦除执行间隔，擦除验证间隔和延迟时间 在所述擦除执行间隔和所述擦除验证间隔之间，其中所述擦除操作改变在所述擦除执行间隔期间施加到字线的字线电压的电平，所述延迟时间的长度，或施加到所述擦除执行间隔的字线电压的电平 延迟时间内的字线。

公开(公告)号：US20120033503A1

公开(公告)日：2012-02-09

申请号：US13176950

申请日：2011-07-06

申请人： JUHYUNG KIM ,  Changseok Kang ,  Hansoo Kim ,  Byeong-In Choe

发明人： JUHYUNG KIM ,  Changseok Kang ,  Hansoo Kim ,  Byeong-In Choe

IPC分类号： G11C16/16

CPC分类号： G11C16/16 ,  G11C16/32

摘要： An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase operation changes a level of a word line voltage applied to word lines during the erase execution interval, a length of the delay time, or a level of the word line voltage applied to the word lines during the delay time.

摘要翻译： 一种电荷捕捉闪存器件的擦除方法，该方法包括接收温度检测结果，并且基于温度检测结果执行擦除操作，其中擦除操作包括擦除执行间隔，擦除验证间隔和延迟时间 在所述擦除执行间隔和所述擦除验证间隔之间，其中所述擦除操作改变在所述擦除执行间隔期间施加到字线的字线电压的电平，所述延迟时间的长度，或施加到所述擦除执行间隔的字线电压的电平 延迟时间内的字线。

公开(公告)号：US20130301350A1

公开(公告)日：2013-11-14

申请号：US13939912

申请日：2013-07-11

申请人： Byeong-In Choe ,  Sung-il Chang ,  Chang-seok Kang ,  Jin-soo Lim

发明人： Byeong-In Choe ,  Sung-il Chang ,  Chang-seok Kang ,  Jin-soo Lim

IPC分类号： H01L29/78 ,  G11C16/04

CPC分类号： H01L29/66666 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.

摘要翻译： 垂直结构的非易失性存储器件可以包括在衬底上沿垂直方向延伸的沟道层。 存储单元串包括沿着沟道层的垂直侧壁在垂直方向上设置在基板上的多个晶体管。 多个晶体管中的至少一个晶体管包括在晶体管的栅极中的至少一个凹部，至少一个包括沟道层的突起延伸到该凹槽中。