摘要:
A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要:
A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要:
A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要:
A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要:
A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要:
A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要:
A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.
摘要翻译:根据本发明的示例性实施方案的薄膜的形成方法包括以大约1.5至大约3W / cm 2的功率密度和处于该范围内的惰性气体的压力形成薄膜 大约0.2至大约0.3Pa。这个过程产生一个非晶金属薄膜阻挡层,防止相邻层的不期望的扩散,即使该阻挡层比许多传统的阻挡层薄。
摘要:
A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.
摘要翻译:根据本发明的示例性实施方式的薄膜形成方法包括以大约1.5至大约3W / cm 2的功率密度形成薄膜,并且在惰性气体的压力范围内 大约0.2至大约0.3Pa。这个过程产生一个非晶金属薄膜阻挡层,防止相邻层的不期望的扩散,即使该阻挡层比许多传统的阻挡层更薄。
摘要:
A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要:
A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.