公开(公告)号：US09502345B2

公开(公告)日：2016-11-22

申请号：US12705846

申请日：2010-02-15

申请人： Sunpil Youn ,  Kwanyoung Oh

发明人： Sunpil Youn ,  Kwanyoung Oh

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/50 ,  H01L24/29 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A multiple-chip-package (MCP) has multiple chip groups and multiple package terminal groups for electrical connections in the MCP. Semiconductor chips of the same chip group are electrically connected to the package terminals of the same package terminal group, while package terminals of different chip groups are electrically connected to the package terminals of different package terminal groups.

摘要翻译： 多芯片封装（MCP）具有多个芯片组和多个封装端子组，用于MCP中的电气连接。 同一芯片组的半导体芯片电连接到同一封装端子组的封装端子，而不同芯片组的封装端子电连接到不同封装端子组的封装端子。

公开(公告)号：US08659136B2

公开(公告)日：2014-02-25

申请号：US12712284

申请日：2010-02-25

申请人： Sunpil Youn ,  Kwanyoung Oh

发明人： Sunpil Youn ,  Kwanyoung Oh

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/50 ,  H01L24/05 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552

摘要： A memory module includes a first multichip package including a first master chip and a first plurality of slave chips, and a second multichip package, the second multichip package including a second master chip and a second plurality of slave chips. A first through via passes through the first master chip and electrically connects to the first master chip to provide a supply voltage to the first master chip. A second through via passes through the first master chip without being electrically connected to provide a supply voltage to the first master chip. A first set of additional through vias pass through respective ones of the first plurality of slave chips and electrically connect to the respective ones of the first plurality of slave chips, wherein the second through via and first set of additional through vias are aligned to form a first stack of through vias.

摘要翻译： 存储器模块包括第一多芯片封装，其包括第一主芯片和第一多个从芯片，以及第二多芯片封装，所述第二多芯片封装包括第二主芯片和第二多个从芯片。 第一通孔通过第一主芯片并电连接到第一主芯片以向第一主芯片提供电源电压。 第二通孔穿过第一主芯片而不被电连接以向第一主芯片提供电源电压。 第一组附加通孔穿过第一多个从芯片中的相应的通孔，并且电连接到第一多个从芯片中的相应的从芯片，其中第二通孔和第一组额外的通孔对齐以形成 第一叠通孔。

公开(公告)号：US20110037158A1

公开(公告)日：2011-02-17

申请号：US12705846

申请日：2010-02-15

申请人： Sunpil Youn ,  Kwanyoung Oh

发明人： Sunpil Youn ,  Kwanyoung Oh

IPC分类号： H01L25/065 ,  H01L23/498

CPC分类号： H01L23/50 ,  H01L24/29 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A multiple-chip-package (MCP) has multiple chip groups and multiple package terminal groups for electrical connections in the MCP. Semiconductor chips of the same chip group are electrically connected to the package terminals of the same package terminal group, while package terminals of different chip groups are electrically connected to the package terminals of different package terminal groups.

摘要翻译： 多芯片封装（MCP）具有多个芯片组和多个封装端子组，用于MCP中的电气连接。 同一芯片组的半导体芯片电连接到同一封装端子组的封装端子，而不同芯片组的封装端子电连接到不同封装端子组的封装端子。

公开(公告)号：US20110156232A1

公开(公告)日：2011-06-30

申请号：US12712284

申请日：2010-02-25

申请人： Sunpil Youn ,  Kwanyoung Oh

发明人： Sunpil Youn ,  Kwanyoung Oh

IPC分类号： H01L25/11

CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/50 ,  H01L24/05 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552

摘要： A module is disclosed. In one embodiment, the module is a memory module including a first multichip package, the first multichip package including a first master chip and a first plurality of slave chips, and a second multichip package, the second multichip package including a second master chip and a second plurality of slave chips. A first through via passes through the first master chip and electrically connects to the first master chip to provide a supply voltage to the first master chip. A second through via passes through the first master chip without being electrically connected to provide a supply voltage to the first master chip. A first set of additional through vias pass through respective ones of the first plurality of slave chips and electrically connect to the respective ones of the first plurality of slave chips, wherein the second through via and first set of additional through vias are aligned to form a first stack of through vias. A third through via passes through the second master chip and electrically connects to the second master chip to provide the supply voltage to the second master chip. A fourth through via passes through the second master chip without being electrically connected to provide a supply voltage to the second master chip. A second set of additional through vias passes through a respective one of the second plurality of slave chips and electrically connects to the respective one of the second plurality of slave chips, wherein the fourth through via and second set of additional through vias are aligned to form a second stack of through vias. A first port is electrically connected to the first and third through vias for providing the supply voltage to the first master chip and the second master chip, and a second port is electrically connected to the first and second stacks of through vias for providing the supply voltage to the first plurality of slave chips and the second plurality of slave chips.