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    METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR OFFLOADING INTERNET PROTOCOL SECURITY (IPSEC) PROCESSING USING AN IPSEC PROXY MECHANISM
    1.
    发明申请
    METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR OFFLOADING INTERNET PROTOCOL SECURITY (IPSEC) PROCESSING USING AN IPSEC PROXY MECHANISM 审中-公开
    使用IPSEC代理机制卸载互联网协议安全（IPSEC）处理的方法，系统和计算机可读介质

    公开(公告)号：US20110113236A1

    公开(公告)日：2011-05-12

    申请号：US12938077

    申请日：2010-11-02

    申请人： Sylvain Chenard ,  Allain Legacy ,  Donald Penney ,  Matthew Peters

    发明人： Sylvain Chenard ,  Allain Legacy ,  Donald Penney ,  Matthew Peters

    IPC分类号： H04L9/00

    CPC分类号： H04L63/164 ,  H04L63/0471 ,  H04L63/0485

    摘要： Methods, systems, and computer readable media for offloading IPsec processing from application hosts using an IPsec proxy mechanism are disclosed. According to one method, at least one of unencrypted, IPsec, and Internet key exchange (IKE) packets transmitted between a first application host and a second application host are intercepted by a network gateway. The network gateway performs all IKE and IPsec-related processing for the at least one unencrypted, IPsec, and IKE packets on behalf of the first application host such that the second application host is unaware that IPsec processing is being performed by the network gateway.

    摘要翻译： 公开了使用IPsec代理机制从应用主机卸载IPsec处理的方法，系统和计算机可读介质。 根据一种方法，在第一应用主机和第二应用主机之间传输的未加密，IPsec和因特网密钥交换（IKE）分组中的至少一个被网关拦截。 网络网关代表第一应用主机对至少一个未加密IPsec和IKE分组执行所有IKE和IPsec相关处理，使得第二应用主机不知道网络网关正在执行IPsec处理。

    METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR ADAPTIVE ASSIGNMENT OF AN ACTIVE SECURITY ASSOCIATION INSTANCE IN A REDUNDANT GATEWAY CONFIGURATION
    3.
    发明申请
    METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR ADAPTIVE ASSIGNMENT OF AN ACTIVE SECURITY ASSOCIATION INSTANCE IN A REDUNDANT GATEWAY CONFIGURATION 有权
    方法，系统和计算机可读介质，用于自动分配冗余网关配置中的活动安全关联实例

    公开(公告)号：US20120304276A1

    公开(公告)日：2012-11-29

    申请号：US13115948

    申请日：2011-05-25

    申请人： Allain Legacy ,  Matthew Peters

    发明人： Allain Legacy ,  Matthew Peters

    IPC分类号： G06F21/00

    CPC分类号： H04L63/0209 ,  H04L63/0428 ,  H04L63/164 ,  H04L67/1027

    摘要： According to one aspect, the subject matter described herein includes a method for communicating an encrypted data packet. The method includes steps occurring at a first gateway node. The method also includes receiving a data packet from a first host. The method further includes determining that a first security association (SA) instance associated with the data packet is in an inactive state. The method further includes identifying a second SA instance that is both associated with the data packet and in an active state. The method further includes forwarding the data packet to the second SA instance.

    摘要翻译： 根据一个方面，本文描述的主题包括用于传送加密数据分组的方法。 该方法包括在第一网关节点处发生的步骤。 该方法还包括从第一主机接收数据分组。 该方法还包括确定与数据分组相关联的第一安全关联（SA）实例处于非活动状态。 该方法还包括识别与数据分组相关联并处于活动状态的第二SA实例。 该方法还包括将数据分组转发到第二SA实例。

    Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement
    4.
    发明授权
    Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement 有权
    数字时钟放置引擎装置和方法，具有占空比校正和正交放置

    公开(公告)号：US09124257B2

    公开(公告)日：2015-09-01

    申请号：US13976945

    申请日：2011-12-29

    申请人： Jayen J. Desai ,  Erin Francom ,  Matthew Peters

    发明人： Jayen J. Desai ,  Erin Francom ,  Matthew Peters

    IPC分类号： H03K5/15 ,  H03K5/156 ,  H03K7/08 ,  H03K9/08 ,  G11C7/22

    CPC分类号： H03K5/1565 ,  G11C7/22 ,  H03K7/08 ,  H03K9/08 ,  H04L7/0037

    摘要： A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal.

    摘要翻译： 数字时钟放置引擎具有调整时钟信号的占空比并且调整时钟信号的上升沿/下降沿的位置的电路​​，用于数据采样或其他操作。 在转发时钟接口实现中，与数据信号一起接收时钟信号，并且接收的时钟信号可能由于各种因素而失真。 为了使接收到的数据信号能够被正确地采样，时钟布置引擎产生具有在所接收的时钟信号的上升沿和下降沿之间放置/定时的上升沿和下降沿的恢复时钟信号。

    DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE CORRECTION AND QUADRATURE PLACEMENT
    5.
    发明申请
    DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE CORRECTION AND QUADRATURE PLACEMENT 有权
    数字时钟放置发动机装置和方法与占空比校正和平移放置

    公开(公告)号：US20140203851A1

    公开(公告)日：2014-07-24

    申请号：US13976945

    申请日：2011-12-29

    申请人： Jayen J. Desai ,  Erin Francom ,  Matthew Peters

    发明人： Jayen J. Desai ,  Erin Francom ,  Matthew Peters

    IPC分类号： H03K5/156

    CPC分类号： H03K5/1565 ,  G11C7/22 ,  H03K7/08 ,  H03K9/08 ,  H04L7/0037

    摘要： A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal.

    摘要翻译： 数字时钟放置引擎具有调整时钟信号的占空比并且调整时钟信号的上升沿/下降沿的位置的电路​​，用于数据采样或其他操作。 在转发时钟接口实现中，与数据信号一起接收时钟信号，并且接收的时钟信号可能由于各种因素而失真。 为了使接收到的数据信号能够被正确地采样，时钟布置引擎产生具有在所接收的时钟信号的上升沿和下降沿之间放置/定时的上升沿和下降沿的恢复时钟信号。