A METHOD OR APPARATUS FOR DETERMINING THE MEMORY USAGE OF A PROGRAM
    1.
    发明申请
    A METHOD OR APPARATUS FOR DETERMINING THE MEMORY USAGE OF A PROGRAM 审中-公开
    一种用于确定程序的内存使用的方法或装置

    公开(公告)号:US20070028243A1

    公开(公告)日:2007-02-01

    申请号:US11456362

    申请日:2006-07-10

    CPC classification number: G06F11/3409 G06F2201/81 G06F2201/87

    Abstract: A method and apparatus for determining the memory usage of a program is disclosed in which a first and second programs are run, the memory-allocation of the second program is increased and the performance of the first or second programs is monitored against predetermined performance criteria. When the performance of the first or second program fails to meet the predetermined performance criteria the memory usage of the first program is recorded.

    Abstract translation: 公开了一种用于确定程序的存储器使用的方法和装置,其中运行第一和第二程序,增加了第二程序的存储器分配,并且针对预定的性能标准来监视第一或第二程序的性能。 当第一或第二程序的执行不能满足预定的性能标准时,记录第一程序的存储器使用。

    Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement
    2.
    发明授权
    Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement 有权
    数字时钟放置引擎装置和方法,具有占空比校正和正交放置

    公开(公告)号:US09124257B2

    公开(公告)日:2015-09-01

    申请号:US13976945

    申请日:2011-12-29

    CPC classification number: H03K5/1565 G11C7/22 H03K7/08 H03K9/08 H04L7/0037

    Abstract: A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal.

    Abstract translation: 数字时钟放置引擎具有调整时钟信号的占空比并且调整时钟信号的上升沿/下降沿的位置的电路​​,用于数据采样或其他操作。 在转发时钟接口实现中,与数据信号一起接收时钟信号,并且接收的时钟信号可能由于各种因素而失真。 为了使接收到的数据信号能够被正确地采样,时钟布置引擎产生具有在所接收的时钟信号的上升沿和下降沿之间放置/定时的上升沿和下降沿的恢复时钟信号。

    DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE CORRECTION AND QUADRATURE PLACEMENT
    3.
    发明申请
    DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE CORRECTION AND QUADRATURE PLACEMENT 有权
    数字时钟放置发动机装置和方法与占空比校正和平移放置

    公开(公告)号:US20140203851A1

    公开(公告)日:2014-07-24

    申请号:US13976945

    申请日:2011-12-29

    CPC classification number: H03K5/1565 G11C7/22 H03K7/08 H03K9/08 H04L7/0037

    Abstract: A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal.

    Abstract translation: 数字时钟放置引擎具有调整时钟信号的占空比并且调整时钟信号的上升沿/下降沿的位置的电路​​,用于数据采样或其他操作。 在转发时钟接口实现中,与数据信号一起接收时钟信号,并且接收的时钟信号可能由于各种因素而失真。 为了使接收到的数据信号能够被正确地采样,时钟布置引擎产生具有在所接收的时钟信号的上升沿和下降沿之间放置/定时的上升沿和下降沿的恢复时钟信号。

    METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR OFFLOADING INTERNET PROTOCOL SECURITY (IPSEC) PROCESSING USING AN IPSEC PROXY MECHANISM
    8.
    发明申请
    METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR OFFLOADING INTERNET PROTOCOL SECURITY (IPSEC) PROCESSING USING AN IPSEC PROXY MECHANISM 审中-公开
    使用IPSEC代理机制卸载互联网协议安全(IPSEC)处理的方法,系统和计算机可读介质

    公开(公告)号:US20110113236A1

    公开(公告)日:2011-05-12

    申请号:US12938077

    申请日:2010-11-02

    CPC classification number: H04L63/164 H04L63/0471 H04L63/0485

    Abstract: Methods, systems, and computer readable media for offloading IPsec processing from application hosts using an IPsec proxy mechanism are disclosed. According to one method, at least one of unencrypted, IPsec, and Internet key exchange (IKE) packets transmitted between a first application host and a second application host are intercepted by a network gateway. The network gateway performs all IKE and IPsec-related processing for the at least one unencrypted, IPsec, and IKE packets on behalf of the first application host such that the second application host is unaware that IPsec processing is being performed by the network gateway.

    Abstract translation: 公开了使用IPsec代理机制从应用主机卸载IPsec处理的方法,系统和计算机可读介质。 根据一种方法,在第一应用主机和第二应用主机之间传输的未加密,IPsec和因特网密钥交换(IKE)分组中的至少一个被网关拦截。 网络网关代表第一应用主机对至少一个未加密IPsec和IKE分组执行所有IKE和IPsec相关处理,使得第二应用主机不知道网络网关正在执行IPsec处理。

Patent Agency Ranking