公开(公告)号：US20240290869A1

公开(公告)日：2024-08-29

申请号：US18643031

申请日：2024-04-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Huang Huang ,  Ming-Jhe Sie ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Shu-Uei Jang ,  An Chyi Wei ,  Shiang-Bau Wang ,  Ryan Chia-Jen Chen

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

公开(公告)号：US12057342B2

公开(公告)日：2024-08-06

申请号：US18064783

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiang-Bau Wang ,  Chun-Hung Lee

IPC分类号： H01L21/762 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L21/76232 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31111 ,  H01L21/31116

摘要： A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

公开(公告)号：US11848240B2

公开(公告)日：2023-12-19

申请号：US17114082

申请日：2020-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Uei Jang ,  Chen-Huang Huang ,  Ryan Chia-Jen Chen ,  Shiang-Bau Wang ,  Shu-Yuan Ku

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

公开(公告)号：US11798939B2

公开(公告)日：2023-10-24

申请号：US16707214

申请日：2019-12-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiang-Bau Wang

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7853

摘要： A method for forming a fin field effect transistor (FinFET) device structure and method for forming the same are provided. The method includes providing a substrate, and forming a fin structure on the substrate. The method also includes forming a protection layer on the sidewalls of the fin structure, and forming a dielectric layer on the fin structure and the protection layer. The method further includes removing a portion of the dielectric layer until a portion of the protection layer is exposed, and removing the exposed portion of the protection layer, such that the sidewalls of a lower portion of the fin structure are covered by the protection layer, and the sidewalls of an upper portion of the fin structure are not covered by the protection layer.

公开(公告)号：US20230113320A1

公开(公告)日：2023-04-13

申请号：US18064783

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co, Ltd.

发明人： Shiang-Bau Wang ,  Chun-Hung Lee

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L21/3105

摘要： A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

公开(公告)号：US20220328656A1

公开(公告)日：2022-10-13

申请号：US17809055

申请日：2022-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiang-Bau Wang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/088

摘要： In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.

公开(公告)号：US11374110B2

公开(公告)日：2022-06-28

申请号：US17026012

申请日：2020-09-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiang-Bau Wang

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/78

摘要： In a gate replacement process, forming a dummy gate and an adjacent structure; In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.

公开(公告)号：US20210351084A1

公开(公告)日：2021-11-11

申请号：US17379469

申请日：2021-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiang-Bau Wang ,  Li-Wei Yin ,  Chen-Huang Huang ,  Ming-Jhe Sie ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

摘要： In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.

公开(公告)号：US20210265487A1

公开(公告)日：2021-08-26

申请号：US17026012

申请日：2020-09-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiang-Bau Wang

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/78

摘要： In a gate replacement process, forming a dummy gate and an adjacent structure; In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.

公开(公告)号：US11056478B2

公开(公告)日：2021-07-06

申请号：US16203755

申请日：2018-11-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiang-Bau Wang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ming-Ching Chang

IPC分类号： H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/027 ,  H01L29/66 ,  H01L21/285

摘要： Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.