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1.
公开(公告)号:US20200091345A1
公开(公告)日:2020-03-19
申请号:US16135108
申请日:2018-09-19
发明人: Wen-Li CHIU , Hsin-Che CHIANG , Chun-Sheng LIANG , Kuo-Hua PAN
IPC分类号: H01L29/78 , H01L29/06 , H01L21/768 , H01L21/8234 , H01L21/033 , H01L29/66
摘要: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap in such a way that the mask layer and the fin structure are separated by an air gap in the gap.
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公开(公告)号:US20180350956A1
公开(公告)日:2018-12-06
申请号:US15629862
申请日:2017-06-22
发明人: Hsin-Che CHIANG , Ju-Yuan TZENG , Chun-Sheng LIANG , Shu-Hui WANG , Chih-Yang YEH , Jeng-Ya David YEH
IPC分类号: H01L29/66 , H01L29/78 , H01L29/423
CPC分类号: H01L29/66795 , H01L29/42364 , H01L29/66545 , H01L29/785
摘要: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.
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公开(公告)号:US20200105577A1
公开(公告)日:2020-04-02
申请号:US16224155
申请日:2018-12-18
发明人: Chun-Sheng LIANG , Wei-Chih KAO , Hsin-Che CHIANG , Kuo-Hua PAN
IPC分类号: H01L21/768 , H01L23/522 , H01L29/66 , H01L29/78
摘要: A semiconductor device includes a substrate, a gate stack over the substrate, an insulating structure over the gate stack, a conductive via in the insulating structure, and an contact etch stop layer (CESL) over the insulating structure. The insulating structure has an air slit therein. The conductive via is electrically connected to the gate stack. A portion of the CESL is exposed in the air slit.
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公开(公告)号:US20160351563A1
公开(公告)日:2016-12-01
申请号:US14724676
申请日:2015-05-28
IPC分类号: H01L27/088 , H01L29/49 , H01L29/51 , H01L21/311 , H01L21/8234 , H01L21/02 , H01L21/762 , H01L29/06 , H01L29/423
CPC分类号: H01L27/088 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/31111 , H01L21/32134 , H01L21/32139 , H01L21/76224 , H01L21/823437 , H01L21/823481 , H01L29/0649 , H01L29/42372 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/518
摘要: A process of manufacturing a semiconductor structure is provided. The process begins with forming a work function metal layer on a substrate, and a hardmask is covered over the work function metal layer. A trench is formed to penetrate the hardmask and the work function metal layer, and an isolation structure is filled in the trench.
摘要翻译: 提供一种制造半导体结构的工艺。 该过程开始于在基底上形成功函数金属层,并且硬掩模覆盖在功函数金属层上。 形成沟槽以穿透硬掩模和功函数金属层,并且隔离结构填充在沟槽中。
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公开(公告)号:US20210296483A1
公开(公告)日:2021-09-23
申请号:US17339020
申请日:2021-06-04
发明人: Ju-Li HUANG , Hsin-Che CHIANG , Yu-Chi PAN , Chun-Ming YANG , Chun-Sheng LIANG , Ying-Liang CHUANG , Ming-Hsi YEG
IPC分类号: H01L29/78 , H01L29/423 , H01L21/285 , H01L29/40 , H01L21/3213 , H01L29/49
摘要: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially coplanar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.
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6.
公开(公告)号:US20190273149A1
公开(公告)日:2019-09-05
申请号:US15909847
申请日:2018-03-01
发明人: Ju-Li HUANG , Chun-Sheng LIANG , Ming-Chi HUANG , Ming-Hsi YEH , Ying-Liang CHUANG , Hsin-Che CHIANG
IPC分类号: H01L29/66 , H01L29/78 , H01L21/311 , H01L21/3213
摘要: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.
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公开(公告)号:US20180342595A1
公开(公告)日:2018-11-29
申请号:US15628740
申请日:2017-06-21
发明人: Hsin-Che CHIANG , Ju-Yuan TZENG , Chun-Sheng LIANG , Shu-Hui WANG , Chih-Yang YEH , Jeng-Ya David YEH
IPC分类号: H01L29/423 , H01L29/49 , H01L27/088 , H01L29/66 , H01L21/8234
摘要: A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.
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公开(公告)号:US20180108653A1
公开(公告)日:2018-04-19
申请号:US15844593
申请日:2017-12-17
IPC分类号: H01L27/088 , H01L21/02 , H01L21/311 , H01L21/762 , H01L21/8234 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/51
摘要: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.
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公开(公告)号:US20200075741A1
公开(公告)日:2020-03-05
申请号:US16678642
申请日:2019-11-08
发明人: Hsin-Che CHIANG , Ju-Yuan TZENG , Chun-Sheng LIANG , Shu-Hui WANG , Chih-Yang YEH , Jeng-Ya David YEH
IPC分类号: H01L29/423 , H01L21/8234 , H01L29/66 , H01L27/088 , H01L29/49
摘要: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.
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公开(公告)号:US20190393326A1
公开(公告)日:2019-12-26
申请号:US16556531
申请日:2019-08-30
发明人: Hsin-Che CHIANG , Ju-Yuan TZENG , Chun-Sheng LIANG , Shu-Hui WANG , Kuo-Hua PAN
IPC分类号: H01L29/66 , H01L21/02 , H01L21/3115 , H01L29/78 , H01L21/28 , H01L29/49 , H01L29/40 , H01L29/51
摘要: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
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