公开(公告)号：US20200083134A1

公开(公告)日：2020-03-12

申请号：US16681687

申请日：2019-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chieh YANG ,  Yung-Chow PENG ,  Chung-Peng HSIEH ,  Sa-Lly LIU

IPC: H01L23/34 ,  H01L49/02 ,  H01L23/522 ,  H01L23/552 ,  H01L23/64

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

公开(公告)号：US20210125890A1

公开(公告)日：2021-04-29

申请号：US17140645

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chieh YANG ,  Yung-Chow PENG ,  Chung-Peng HSIEH ,  Sa-Lly LIU

IPC: H01L23/34 ,  H01L23/64 ,  H01L23/552 ,  H01L23/522 ,  H01L49/02

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

公开(公告)号：US20150249051A1

公开(公告)日：2015-09-03

申请号：US14712940

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming Hsien TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Sa-Lly LIU ,  Fu-Lung HSUEH

IPC: H01L23/522 ,  H03F1/26 ,  H01L23/58 ,  H03F3/04 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/092 ,  H01L28/10 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/04 ,  H03F2200/294 ,  H03F2200/372 ,  H01L2924/00

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract translation: 三维（3D）电路包括包括半导体衬底的第一层，与第一层相邻设置的第二层，包括电感元件部分的三维电感器，电感元件部分包括从第一层延伸到 第二层的介电层。 3D电路包括围绕导电通孔的至少一部分的接地屏蔽。 在一些实施例中，接地屏蔽包括中空圆柱形笼。 在一些实施例中，3D电路是低噪声放大器。

公开(公告)号：US20140256063A1

公开(公告)日：2014-09-11

申请号：US14280732

申请日：2014-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Lin YANG ,  Jun-De JIN ,  Fu-Lung HSUEH ,  Sa-Lly LIU ,  Tong-Chern ONG ,  Chun-Jung LIN ,  Ya-Chen KAO

IPC: H01L25/065 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01F5/00 ,  H01F27/2804 ,  H01F41/046 ,  H01F2027/2809 ,  H01L23/48 ,  H01L23/5227 ,  H01L2225/06531 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

Abstract translation: 通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。 第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。 铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。

公开(公告)号：US20130302942A1

公开(公告)日：2013-11-14

申请号：US13945169

申请日：2013-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Lin YANG ,  Sa-Lly LIU ,  Chien-Min LIN

IPC: H01L23/00

CPC classification number: H01L24/82 ,  H01L23/3677 ,  H01L23/48 ,  H01L23/5227 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: A package comprises a die stack having at least two stacked dies coupled for contactless communications with each other. At least one of the stacked dies has a substrate joined to its major face. The substrate has a plurality of conductive traces in or on the substrate for conducting power to the dies and for conducting heat from the dies. At least one conductive pillar is joined to at least one of the conductive traces on at least a first edge of the substrate, for conducting power to the at least one die and for conducting heat from the at least one die.